Model { Name "maf" Version 6.1 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.197" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "ibm-5348_P100-1997" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Mon Oct 10 11:36:59 2005" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "umb" ModifiedDateFormat "%" LastModifiedDate "Tue Feb 20 15:44:16 2007" ModelVersionFormat "1.%" ConfigurationManager "None" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on StrictBusMsg "None" ProdHWDeviceType "32-bit Generic" ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.0.4" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.0.4" StartTime "0.0" StopTime "15000" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" RelTol "1e-3" SolverMode "SingleTasking" Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" ZeroCrossControl "UseLocalSettings" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" RateTranMode "Deterministic" } Simulink.DataIOCC { $ObjectID 3 Version "1.0.4" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.0.4" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on ConditionalExecOptimization "on_for_testing" InlineParams off InlineInvariantSignals on OptimizeBlockIOStorage on BufferReuse on EnforceIntegerDowncast on ExpressionFolding on FoldNonRolledExpr on LocalBlockOutputs on ParameterPooling on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off OptimizeModelRefInitCode off LifeSpan "inf" } Simulink.DebuggingCC { $ObjectID 5 Version "1.0.4" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.0.4" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.0.4" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.0.4" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 9 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" PropName "DisabledProps" } Version "1.0.4" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off PrefixModelToSubsysFcnNames on CustomSymbolStr "$R$N$M" MangleLength 1 DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 12 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" PropName "DisabledProps" } Version "1.0.4" TargetFcnLib "ansi_tfl_tmw.mat" GenFloatMathFcnCalls "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off IsPILTarget off ModelReferenceCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" SimulationMode "normal" CurrentDlgPage "Solver" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 14 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType BusCreator Inputs "4" DisplayOption "none" BusObject "BusObject" NonVirtualBus off } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Inport BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Outport Port "1" BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType "S-Function" FunctionName "system" SFunctionModules "''" PortCounts "[]" } Block { BlockType Sin SineType "Time based" TimeSource "Use simulation time" Amplitude "1" Bias "0" Frequency "1" Phase "0" Samples "10" Offset "0" SampleTime "-1" VectorParams1D on } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" PermitHierarchicalResolution "All" SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Terminator } Block { BlockType ToWorkspace VariableName "simulink_output" MaxDataPoints "1000" Decimation "1" SampleTime "0" FixptAsFi off } Block { BlockType UniformRandomNumber Minimum "-1" Maximum "1" Seed "0" SampleTime "-1" VectorParams1D on } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "maf" Location [2, 78, 998, 732] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "86" ReportName "simulink-default.rpt" Block { BlockType Reference Name " System Generator" Tag "genX" Ports [] Position [87, 458, 138, 508] ShowName off AttributesFormatString "System\\nGenerator" UserDataPersistent on UserData "DataTag0" FontSize 10 SourceBlock "xbsIndex_r3/ System Generator" SourceType "Xilinx System Generator" ShowPortLabels on xilinxfamily "Virtex2" part "xc2v1000" speed "-4" package "bg575" synthesis_tool "XST" directory "./netlist" testbench off simulink_period "1" sysclk_period "100" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" } Block { BlockType SubSystem Name "4-Input Adder" Ports [4, 1] Position [478, 510, 657, 575] Orientation "down" NamePlacement "alternate" TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "4-Input Adder" Location [482, 489, 761, 677] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "99" Block { BlockType Inport Name "In1" Position [25, 25, 55, 40] Orientation "down" Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "In2" Position [50, 25, 80, 40] Orientation "down" Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "In3" Position [140, 25, 170, 40] Orientation "down" Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "In4" Position [225, 25, 255, 40] Orientation "down" Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "AddSub3" Ports [2, 1] Position [27, 75, 78, 125] Orientation "down" NamePlacement "alternate" FontSize 10 SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AddSub4" Ports [2, 1] Position [117, 75, 168, 125] Orientation "down" NamePlacement "alternate" FontSize 10 SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AddSub5" Ports [2, 1] Position [202, 75, 253, 125] Orientation "down" NamePlacement "alternate" FontSize 10 SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Outport Name "Out1" Position [215, 150, 245, 165] Orientation "down" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "AddSub3" SrcPort 1 Points [0, 10; 45, 0; 0, -90; 30, 0] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [0, 10; 45, 0; 0, -90; 25, 0] DstBlock "AddSub5" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 DstBlock "AddSub3" DstPort 1 } Line { SrcBlock "In2" SrcPort 1 DstBlock "AddSub3" DstPort 2 } Line { SrcBlock "In3" SrcPort 1 DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "In4" SrcPort 1 DstBlock "AddSub5" DstPort 2 } Line { SrcBlock "AddSub5" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType Reference Name "AMP1" Ports [1, 1] Position [250, 217, 305, 273] FontSize 10 SourceBlock "xbsIndex_r3/CMult" SourceType "Xilinx Constant Multiplier" const ".2" show_cparam on const_n_bits "16" const_bin_pt "10" show_output_param off precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "6" quantization "Round (unbiased: +/- Inf)" overflow "Wrap" latency "0" explicit_period off period "1" en off dbl_ovrd off show_param off mult_type "Parallel" oversample "2" mem_type "Distributed RAM" pipeline off use_rpm on placement_style "Rectangular Shape" gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AMP2" Ports [1, 1] Position [845, 472, 900, 528] FontSize 10 SourceBlock "xbsIndex_r3/CMult" SourceType "Xilinx Constant Multiplier" const "1" show_cparam on const_n_bits "16" const_bin_pt "8" show_output_param off precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "6" quantization "Round (unbiased: +/- Inf)" overflow "Wrap" latency "0" explicit_period off period "1" en off dbl_ovrd off show_param off mult_type "Parallel" oversample "2" mem_type "Distributed RAM" pipeline off use_rpm on placement_style "Rectangular Shape" gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AddSub1" Ports [2, 1] Position [335, 207, 385, 258] FontSize 10 SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" use_carryin off use_carryout off en off dbl_ovrd off show_param off use_core on pipeline off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType BusCreator Name "Bus\nCreator1" Ports [4, 1] Position [960, 239, 980, 426] ShowName off DialogController "Simulink.DDGSource_Bus" DisplayOption "bar" Port { PortNumber 1 Name "Delay Taps" PropagatedSignals "Sine + Noise, , , " RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType Reference Name "Delay1" Ports [1, 1] Position [455, 377, 500, 423] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay2" Ports [1, 1] Position [545, 377, 590, 423] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay3" Ports [1, 1] Position [635, 377, 680, 423] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType ToWorkspace Name "FilteredOutput1" Position [1085, 485, 1145, 515] VariableName "d" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "Gateway In" Ports [1, 1] Position [150, 64, 205, 86] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Signed (2's comp)" n_bits "16" bin_pt "8" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway In1" Ports [1, 1] Position [150, 144, 205, 166] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Signed (2's comp)" n_bits "16" bin_pt "8" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out" Ports [1, 1] Position [705, 64, 760, 86] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off Port { PortNumber 1 Name "Sine Wave" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType Reference Name "Gateway Out2" Ports [1, 1] Position [705, 144, 760, 166] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off Port { PortNumber 1 Name "Noise" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType Reference Name "Gateway Out3" Ports [1, 1] Position [705, 224, 760, 246] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off Port { PortNumber 1 Name "Sine + Noise" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType Reference Name "Gateway Out4" Ports [1, 1] Position [945, 489, 1000, 511] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off Port { PortNumber 1 Name "Filtered Output" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType UniformRandomNumber Name "Noise" Position [50, 131, 100, 179] SampleTime "0" } Block { BlockType ToWorkspace Name "Noise1" Position [935, 90, 995, 120] VariableName "b" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "Resource Estimator" Tag "resEstTag" Ports [] Position [201, 453, 254, 506] ShowName off AttributesFormatString "Resource\\nEstimator" FontName "Arial" FontSize 10 SourceBlock "xbsIndex_r3/Resource Estimator" SourceType "Xilinx Resource Estimator Block" ShowPortLabels on xl_estimator_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_estimator_area off simulink_period "1" mrp_directory "D:/matlabR12/toolbox/xilinx/sysgen/bin" } Block { BlockType Scope Name "Scope" Ports [5] Position [1085, 35, 1155, 435] Location [119, 57, 932, 694] Open off NumInputPorts "5" TickLabels "on" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" } TimeRange "300" YMin "-1~-1~-2~-1.5~-2" YMax "1~1~2~1.5~2" DataFormat "StructureWithTime" MaxDataPoints "300" } Block { BlockType Sin Name "Sine Wave" Ports [0, 1] Position [50, 51, 100, 99] SineType "Sample based" Samples "55" SampleTime "1" } Block { BlockType ToWorkspace Name "SineAndNoise1" Position [935, 185, 995, 215] NamePlacement "alternate" VariableName "c" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "SineWave1" Position [935, 15, 995, 45] VariableName "a" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "tap2" Ports [1, 1] Position [540, 299, 595, 321] NamePlacement "alternate" SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "tap3" Ports [1, 1] Position [630, 344, 685, 366] NamePlacement "alternate" SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "tap4" Ports [1, 1] Position [745, 389, 800, 411] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Line { Name "Sine Wave" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 Points [0, 0; 130, 0] Branch { Labels [1, 0] DstBlock "Scope" DstPort 1 } Branch { Points [0, -45] DstBlock "SineWave1" DstPort 1 } } Line { SrcBlock "Gateway In" SrcPort 1 Points [0, 0; 105, 0] Branch { DstBlock "Gateway Out" DstPort 1 } Branch { Points [0, 145] DstBlock "AddSub1" DstPort 1 } } Line { SrcBlock "Sine Wave" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Noise" SrcPort 1 DstBlock "Gateway In1" DstPort 1 } Line { Name "Noise" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [0, 0; 130, 0] Branch { Labels [1, 0] DstBlock "Scope" DstPort 2 } Branch { Points [0, -50] DstBlock "Noise1" DstPort 1 } } Line { Name "Filtered Output" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [0, 0; 40, 0] Branch { DstBlock "FilteredOutput1" DstPort 1 } Branch { Labels [1, 0] Points [0, -105] DstBlock "Scope" DstPort 5 } } Line { SrcBlock "Delay3" SrcPort 1 Points [0, 0; 20, 0] Branch { DstBlock "tap4" DstPort 1 } Branch { Points [0, 85; -70, 0] DstBlock "4-Input Adder" DstPort 4 } } Line { SrcBlock "AMP2" SrcPort 1 DstBlock "Gateway Out4" DstPort 1 } Line { SrcBlock "Gateway In1" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, 90] DstBlock "AMP1" DstPort 1 } Branch { DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, -90] DstBlock "tap2" DstPort 1 } Branch { Points [0, 60; 25, 0] DstBlock "4-Input Adder" DstPort 2 } } Line { SrcBlock "Delay2" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [0, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, -45] DstBlock "tap3" DstPort 1 } } Branch { Points [0, 60; -20, 0] DstBlock "4-Input Adder" DstPort 3 } } Line { SrcBlock "tap4" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 4 } Line { Name "Delay Taps" Labels [3, 0] SrcBlock "Bus\nCreator1" SrcPort 1 Points [30, 0; 0, -20] DstBlock "Scope" DstPort 4 } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 0; 30, 0] Branch { DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, 165] Branch { DstBlock "Delay1" DstPort 1 } Branch { Points [0, 85; 80, 0] DstBlock "4-Input Adder" DstPort 1 } } } Line { Name "Sine + Noise" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [0, 0; 130, 0] Branch { Points [0, 30] Branch { Points [0, -65] DstBlock "SineAndNoise1" DstPort 1 } Branch { Labels [1, 0] DstBlock "Bus\nCreator1" DstPort 1 } } Branch { DstBlock "Scope" DstPort 3 } } Line { SrcBlock "AMP1" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "4-Input Adder" SrcPort 1 Points [0, 25; 200, 0; 0, -105] DstBlock "AMP2" DstPort 1 } Line { SrcBlock "tap2" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 2 } Line { SrcBlock "tap3" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 3 } Annotation { Name "Design Name: Lab5 FIR - 4-input MAF\nDesigner:" "\nDate:\nVersion:" Position [424, 715] HorizontalAlignment "left" DropShadow on FontName "Arial" FontSize 22 } } } MatData { NumRecords 1 DataRecord { Tag DataTag0 Data " %)30 . 2 @ 8 ( @ % " "\" $ ! 0 % 0 !@ $ & 7, !V86QU97, . < 8 ( 0 % \" $ ! " " 0 . 0 8 ( ! % \" $ + 0 " "0 \"P $A$3\"!.971L:7-T . : 8 ( 0 % \" " " $ ! 0 . . 8 ( ! % \" $ ' " "0 0 !P '1A7-T96T #@ $@ & \" " " 0 !0 @ ! & $ $ !@ !!8V-O0 !T97-T8F5N8V@ #( #@" " #@ & \" 0 !0 @ ! \" $ $ @ !X8" "S)V,3 P, X P !@ @ $ 4 ( 0 ( ! ! @" " M- #@ #@ & \" 0 !0 @ ! !0 $ $ " "4 !B9S4W-0 X P !@ @ $ 4 ( 0 , ! " " ! P!84U0 #@ $ & \" 0 !0 @ ! \"0 $ " " $ D N+VYE=&QI