Model { Name "lab1inc" Version 6.0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.141" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "ibm-5348_P100-1997" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Tue Jun 21 08:08:39 2005" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "Administrator" ModifiedDateFormat "%" LastModifiedDate "Tue Nov 14 10:49:57 2006" ModelVersionFormat "1.%" ConfigurationManager "None" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ProdHWDeviceType "32-bit Generic" ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.0.4" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.0.4" StartTime "0.0" StopTime "5000" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" RelTol "1e-3" SolverMode "SingleTasking" Solver "FixedStepDiscrete" ZeroCrossControl "UseLocalSettings" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" RateTranMode "Deterministic" } Simulink.DataIOCC { $ObjectID 3 Version "1.0.4" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.0.4" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on ConditionalExecOptimization "on_for_testing" InlineParams off InlineInvariantSignals on OptimizeBlockIOStorage on BufferReuse on EnforceIntegerDowncast on ExpressionFolding on FoldNonRolledExpr on LocalBlockOutputs on ParameterPooling on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off OptimizeModelRefInitCode off LifeSpan "inf" } Simulink.DebuggingCC { $ObjectID 5 Version "1.0.4" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" SolverPrmCheckMsg "none" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.0.4" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.0.4" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.0.4" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 9 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" PropName "DisabledProps" } Version "1.0.4" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off PrefixModelToSubsysFcnNames on CustomSymbolStr "$R$N$M" MangleLength 1 DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 12 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" PropName "DisabledProps" } Version "1.0.4" TargetFcnLib "ansi_tfl_tmw.mat" GenFloatMathFcnCalls "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off IsPILTarget off ModelReferenceCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" SimulationMode "normal" CurrentDlgPage "Solver" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 14 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Clock DisplayTime off } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Fcn Expr "sin(u[1])" SampleTime "-1" } Block { BlockType SignalConversion OverrideOpt off } Block { BlockType Inport BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Lookup InputValues "[-4:5]" OutputValues " rand(1,10)-0.5" LookUpMeth "Interpolation-Extrapolation" OutDataTypeMode "Same as input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" LUTDesignTableMode "Redesign Table" LUTDesignDataSource "Block Dialog" LUTDesignFunctionName "sqrt(x)" LUTDesignUseExistingBP on LUTDesignRelError "0.01" LUTDesignAbsError "1e-6" } Block { BlockType Outport Port "1" BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Reference } Block { BlockType "S-Function" FunctionName "system" PortCounts "[]" SFunctionModules "''" } Block { BlockType Step Time "1" Before "0" After "1" SampleTime "-1" VectorParams1D on ZeroCross on } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" PermitHierarchicalResolution "All" SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Terminator } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 14 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 14 FontWeight "normal" FontAngle "normal" } System { Name "lab1inc" Location [2, 75, 998, 728] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "64" ReportName "simulink-default.rpt" Block { BlockType Reference Name " SINE table" Ports [1, 1] Position [550, 284, 600, 336] FontSize 10 SourceBlock "xbsIndex_r3/ROM" SourceType "Xilinx Single Port Read-Only Memory" depth "256" initVector "127*sin( [0:2*pi/2^8:2*pi])+128" arith_type "Unsigned" n_bits "8" bin_pt "0" latency "0" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param on distributed_mem on use_rpm off gen_core off xl_area "[2 0 0 3 0 0 0]" xl_use_area off } Block { BlockType Reference Name " System Generator" Tag "genX" Ports [] Position [79, 160, 130, 210] ShowName off AttributesFormatString "System\\nGenerator" UserDataPersistent on UserData "DataTag0" FontSize 10 SourceBlock "xbsIndex_r3/ System Generator" SourceType "Xilinx System Generator" ShowPortLabels on xilinxfamily "Spartan3" part "xc3s200" speed "-5" package "ft256" synthesis_tool "XST" directory "C:/Documents and Settings/Administrator/Desktop" "/DSP FPGA Labs/lab1ad" testbench off simulink_period "1" sysclk_period "100" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" } Block { BlockType Reference Name "AD0" Ports [1, 1] Position [135, 509, 190, 531] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Boolean" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "AD1" Ports [1, 1] Position [130, 564, 185, 586] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Boolean" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "ADCLK" Ports [1, 1] Position [1315, 889, 1370, 911] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "ADCS" Ports [1, 1] Position [1315, 789, 1370, 811] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType SubSystem Name "CLK_DA_AD" Ports [5, 6] Position [735, 521, 855, 684] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "CLK_DA_AD" Location [2, 74, 1014, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "AD0_in" Position [295, 433, 325, 447] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "AD1_in" Position [295, 498, 325, 512] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "DA0_in" Position [335, 103, 365, 117] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "DA1_in" Position [335, 158, 365, 172] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "clk_reset" Position [15, 278, 45, 292] Port "5" IconDisplay "Port number" LatchInput off } Block { BlockType SubSystem Name "AD ser2para" Ports [4, 2] Position [490, 309, 635, 496] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "AD ser2para" Location [-126, 549, 629, 1184] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "ENA" Position [15, 38, 45, 52] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Sample" Position [685, 715, 715, 730] Orientation "up" Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "AD0_in" Position [40, 683, 70, 697] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "AD1_in" Position [40, 603, 70, 617] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Concat1" Ports [8, 1] Position [340, 74, 385, 661] FontSize 10 SourceBlock "xbsIndex_r3/Concat" SourceType "Xilinx Bus Concatenator" num_inputs "8" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Concat2" Ports [8, 1] Position [600, 79, 645, 666] FontSize 10 SourceBlock "xbsIndex_r3/Concat" SourceType "Xilinx Bus Concatenator" num_inputs "8" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Delay1" Ports [2, 1] Position [505, 84, 550, 131] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay11" Ports [2, 1] Position [245, 79, 290, 126] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay12" Ports [2, 1] Position [240, 149, 285, 196] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay13" Ports [2, 1] Position [240, 224, 285, 271] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay14" Ports [2, 1] Position [240, 299, 285, 346] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay15" Ports [2, 1] Position [240, 374, 285, 421] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay16" Ports [2, 1] Position [240, 449, 285, 496] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay17" Ports [2, 1] Position [240, 524, 285, 571] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay18" Ports [2, 1] Position [240, 599, 285, 646] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "8" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay19" Ports [2, 1] Position [745, 524, 790, 571] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay2" Ports [2, 1] Position [500, 154, 545, 201] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay3" Ports [2, 1] Position [500, 229, 545, 276] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay4" Ports [2, 1] Position [500, 304, 545, 351] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay5" Ports [2, 1] Position [500, 379, 545, 426] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay6" Ports [2, 1] Position [500, 454, 545, 501] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay7" Ports [2, 1] Position [500, 529, 545, 576] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay8" Ports [2, 1] Position [500, 604, 545, 651] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "8" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay9" Ports [2, 1] Position [720, 364, 765, 411] FontSize 10 SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Inverter1" Ports [1, 1] Position [85, 27, 135, 63] NamePlacement "alternate" SourceBlock "xbsIndex_r3/Inverter" SourceType "Xilinx Inverter" latency "0" explicit_period "off" period "1" en "off" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Outport Name "AD0_out" Position [790, 383, 820, 397] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "AD1_out" Position [815, 543, 845, 557] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "ENA" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 Points [10, 0; 0, 310; 270, 0; 0, -145] DstBlock "Delay19" DstPort 1 } Line { SrcBlock "Delay18" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -40; -75, 0] DstBlock "Delay17" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat1" DstPort 8 } } Line { SrcBlock "Delay12" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -30; -75, 0; 0, -55] DstBlock "Delay11" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat1" DstPort 2 } } Line { SrcBlock "Delay13" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay12" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat1" DstPort 3 } } Line { SrcBlock "Delay14" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay13" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat1" DstPort 4 } } Line { SrcBlock "Delay15" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay14" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat1" DstPort 5 } } Line { SrcBlock "Delay16" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay15" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat1" DstPort 6 } } Line { SrcBlock "Delay17" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay16" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat1" DstPort 7 } } Line { SrcBlock "Delay11" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Delay8" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -40; -75, 0] DstBlock "Delay7" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat2" DstPort 8 } } Line { SrcBlock "Delay2" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -30; -75, 0; 0, -55] DstBlock "Delay1" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat2" DstPort 2 } } Line { SrcBlock "Delay3" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay2" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat2" DstPort 3 } } Line { SrcBlock "Delay4" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay3" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat2" DstPort 4 } } Line { SrcBlock "Delay5" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay4" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat2" DstPort 5 } } Line { SrcBlock "Delay6" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay5" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat2" DstPort 6 } } Line { SrcBlock "Delay7" SrcPort 1 Points [0, 0; 10, 0] Branch { Points [0, -35; -80, 0; 0, -55] DstBlock "Delay6" DstPort 1 } Branch { Points [0, 5] DstBlock "Concat2" DstPort 7 } } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "Delay9" DstPort 1 } Line { SrcBlock "Sample" SrcPort 1 Points [0, 0; 0, -15] Branch { Points [30, 0] DstBlock "Delay19" DstPort 2 } Branch { Points [0, -295] DstBlock "Delay9" DstPort 2 } } Line { SrcBlock "Delay9" SrcPort 1 DstBlock "AD0_out" DstPort 1 } Line { SrcBlock "Delay19" SrcPort 1 DstBlock "AD1_out" DstPort 1 } Line { SrcBlock "AD1_in" SrcPort 1 DstBlock "Delay18" DstPort 1 } Line { SrcBlock "AD0_in" SrcPort 1 Points [360, 0; 0, -75] DstBlock "Delay8" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [40, 0; 0, -15] Branch { Points [275, 0; 0, 90] Branch { Points [0, 70] Branch { Points [0, 75] Branch { Points [0, 75] Branch { Points [0, 70] Branch { Points [0, 80] Branch { Points [0, 75] Branch { DstBlock "Delay7" DstPort 2 } Branch { Points [0, 75] DstBlock "Delay8" DstPort 2 } } Branch { DstBlock "Delay6" DstPort 2 } } Branch { Points [0, 5] DstBlock "Delay5" DstPort 2 } } Branch { DstBlock "Delay4" DstPort 2 } } Branch { DstBlock "Delay3" DstPort 2 } } Branch { DstBlock "Delay2" DstPort 2 } } Branch { DstBlock "Delay1" DstPort 2 } } Branch { Points [0, 85] Branch { Points [0, 70] Branch { Points [0, 75] Branch { Points [0, 75] Branch { Points [0, 70] Branch { Points [0, 80] Branch { Points [0, 75] Branch { DstBlock "Delay17" DstPort 2 } Branch { Points [0, 75] DstBlock "Delay18" DstPort 2 } } Branch { DstBlock "Delay16" DstPort 2 } } Branch { Points [45, 0] DstBlock "Delay15" DstPort 2 } } Branch { DstBlock "Delay14" DstPort 2 } } Branch { DstBlock "Delay13" DstPort 2 } } Branch { DstBlock "Delay12" DstPort 2 } } Branch { DstBlock "Delay11" DstPort 2 } } } } } Block { BlockType SubSystem Name "ADA Clock Generation" Ports [1, 5] Position [150, 161, 270, 409] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "ADA Clock Generation" Location [315, 118, 953, 627] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "reset" Position [15, 43, 45, 57] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Constant1" Ports [0, 1] Position [145, 240, 190, 270] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "0" equ "P=C" arith_type "Unsigned" n_bits "6" bin_pt "1" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Constant2" Ports [0, 1] Position [145, 170, 190, 200] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "2" equ "P=C" arith_type "Unsigned" n_bits "6" bin_pt "1" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Constant3" Ports [0, 1] Position [145, 315, 190, 345] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "2" equ "P=C" arith_type "Unsigned" n_bits "6" bin_pt "1" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Constant4" Ports [0, 1] Position [145, 95, 190, 125] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const ".5" equ "P=C" arith_type "Unsigned" n_bits "6" bin_pt "1" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Expression" Ports [2, 1] Position [360, 163, 410, 212] FontSize 10 SourceBlock "xbsIndex_r3/Expression" SourceType "Xilinx Expression Block" expression "a & b" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp "on" latency "0" explicit_period "off" period "1" en "off" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "FSM Counter" Ports [1, 1] Position [90, 24, 140, 76] SourceBlock "xbsIndex_r3/Counter" SourceType "Xilinx Counter Block" cnt_type "Count Limited" n_bits "6" bin_pt "1" arith_type "Unsigned" start_count "0" cnt_to "17" cnt_by_val ".5" operation "Up" explicit_period "off" period "1" load_pin "off" rst "on" en "off" dbl_ovrd "off" show_param "off" use_rpm "on" gen_core "off" xl_area "[3 3 0 4 0 0 0]" xl_use_area "off" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [395, 233, 445, 267] Orientation "left" SourceBlock "xbsIndex_r3/Inverter" SourceType "Xilinx Inverter" latency "0" explicit_period "off" period "1" en "off" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Register" Ports [2, 1] Position [395, 303, 440, 352] FontSize 10 SourceBlock "xbsIndex_r3/Register" SourceType "Xilinx Register Block" init "0" reg_only_valid "off" explicit_period "on" period "1" rst "on" en "off" out_en "off" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "State=CONVERT" Ports [2, 1] Position [255, 298, 300, 342] FontSize 10 SourceBlock "xbsIndex_r3/Relational" SourceType "Xilinx Relational Block" mode "ab" latency "1" explicit_period "off" period "1" en "off" dbl_ovrd "off" show_param "off" xl_area "[1 0 0 1 0 0 0]" xl_use_area "off" } Block { BlockType Reference Name "State=SYNC1" Ports [2, 1] Position [255, 153, 300, 197] FontSize 10 SourceBlock "xbsIndex_r3/Relational" SourceType "Xilinx Relational Block" mode "a>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Constant 1" Ports [0, 1] Position [865, 185, 910, 215] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "0" equ "P=C" arith_type "Unsigned" n_bits "1" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Mux" Ports [19, 1] Position [435, 124, 490, 746] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "18" precision "User Defined" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "1" explicit_period "off" period "1" en "off" dbl_ovrd "off" show_param "off" mux_type "off" use_rpm "off" gen_core "off" xl_area "[4 0 0 8 0 0 0]" xl_use_area "off" } Block { BlockType Reference Name "Mux1" Ports [19, 1] Position [1050, 96, 1110, 774] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "18" precision "User Defined" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "1" explicit_period "off" period "1" en "off" dbl_ovrd "off" show_param "off" mux_type "off" use_rpm "off" gen_core "off" xl_area "[4 0 0 8 0 0 0]" xl_use_area "off" } Block { BlockType Reference Name "Slice1" Ports [1, 1] Position [285, 461, 330, 489] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice10" Ports [1, 1] Position [135, 711, 180, 739] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-7" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice11" Ports [1, 1] Position [905, 476, 950, 504] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice12" Ports [1, 1] Position [750, 726, 795, 754] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-7" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice14" Ports [1, 1] Position [835, 516, 880, 544] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-1" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice15" Ports [1, 1] Position [785, 546, 830, 574] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-2" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice16" Ports [1, 1] Position [735, 586, 780, 614] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-3" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice17" Ports [1, 1] Position [920, 616, 965, 644] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-4" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice18" Ports [1, 1] Position [855, 651, 900, 679] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-5" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice19" Ports [1, 1] Position [805, 686, 850, 714] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-6" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice2" Ports [1, 1] Position [351, 75, 379, 120] Orientation "down" NamePlacement "alternate" SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "5" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice3" Ports [1, 1] Position [220, 496, 265, 524] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-1" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice4" Ports [1, 1] Position [165, 531, 210, 559] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-2" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice5" Ports [1, 1] Position [115, 571, 160, 599] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-3" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice7" Ports [1, 1] Position [300, 601, 345, 629] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-4" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice8" Ports [1, 1] Position [235, 636, 280, 664] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-5" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Reference Name "Slice9" Ports [1, 1] Position [185, 671, 230, 699] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "-6" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output "off" explicit_period "off" period "1" dbl_ovrd "off" } Block { BlockType Outport Name "DA0_out" Position [515, 428, 545, 442] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "DA1_out" Position [1135, 428, 1165, 442] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "Constant 0" SrcPort 1 Points [0, 0; 65, 0] Branch { Points [60, 0] DstBlock "Mux" DstPort 2 } Branch { Points [0, 10] Branch { Points [0, 35] Branch { Points [60, 0] DstBlock "Mux" DstPort 4 } Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [60, 0] DstBlock "Mux" DstPort 6 } Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [60, 0] DstBlock "Mux" DstPort 8 } Branch { Points [0, 35] Branch { DstBlock "Mux" DstPort 9 } Branch { Points [0, 30] Branch { DstBlock "Mux" DstPort 10 } Branch { Points [0, 30] DstBlock "Mux" DstPort 11 } } } } Branch { Points [60, 0] DstBlock "Mux" DstPort 7 } } } Branch { Points [60, 0] DstBlock "Mux" DstPort 5 } } } Branch { Points [60, 0] DstBlock "Mux" DstPort 3 } } } Line { SrcBlock "Slice2" SrcPort 1 Points [0, 0; 35, 0] Branch { Points [20, 0] DstBlock "Mux" DstPort 1 } Branch { Points [0, -5] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "DA0_in" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [0, 25] Branch { Points [0, 35] Branch { Points [0, 30] Branch { Points [0, 5] DstBlock "Slice9" DstPort 1 } Branch { Points [0, 45] DstBlock "Slice10" DstPort 1 } } Branch { DstBlock "Slice8" DstPort 1 } } Branch { DstBlock "Slice7" DstPort 1 } } Branch { Points [0, -5] Branch { DstBlock "Slice5" DstPort 1 } Branch { Points [0, -40] Branch { DstBlock "Slice4" DstPort 1 } Branch { Points [0, -35] Branch { Points [0, -35] DstBlock "Slice1" DstPort 1 } Branch { DstBlock "Slice3" DstPort 1 } } } } } Line { SrcBlock "Constant 1" SrcPort 1 Points [0, 0; 65, 0] Branch { Points [55, 0] DstBlock "Mux1" DstPort 2 } Branch { Points [0, 10] Branch { Points [0, 35] Branch { Points [0, -20] DstBlock "Mux1" DstPort 4 } Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, -20] DstBlock "Mux1" DstPort 6 } Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, -20] DstBlock "Mux1" DstPort 8 } Branch { Points [0, 35] Branch { Points [0, -20] DstBlock "Mux1" DstPort 9 } Branch { Points [0, 20] Branch { Points [55, 0] DstBlock "Mux1" DstPort 10 } Branch { Points [0, 30] DstBlock "Mux1" DstPort 11 } } } } Branch { Points [0, -20] DstBlock "Mux1" DstPort 7 } } } Branch { Points [0, -20] DstBlock "Mux1" DstPort 5 } } } Branch { Points [0, -20] DstBlock "Mux1" DstPort 3 } } } Line { SrcBlock "Slice1" SrcPort 1 Points [40, 0; 0, 20] DstBlock "Mux" DstPort 12 } Line { SrcBlock "Slice3" SrcPort 1 Points [75, 0; 0, 15] DstBlock "Mux" DstPort 13 } Line { SrcBlock "Slice4" SrcPort 1 Points [100, 0; 0, 10] DstBlock "Mux" DstPort 14 } Line { SrcBlock "Slice5" SrcPort 1 DstBlock "Mux" DstPort 15 } Line { SrcBlock "Slice7" SrcPort 1 DstBlock "Mux" DstPort 16 } Line { SrcBlock "Slice8" SrcPort 1 Points [65, 0; 0, -5] DstBlock "Mux" DstPort 17 } Line { SrcBlock "Slice9" SrcPort 1 Points [90, 0; 0, -10] DstBlock "Mux" DstPort 18 } Line { SrcBlock "Slice10" SrcPort 1 Points [115, 0; 0, -20] DstBlock "Mux" DstPort 19 } Line { SrcBlock "Slice11" SrcPort 1 Points [15, 0; 0, 15] DstBlock "Mux1" DstPort 12 } Line { SrcBlock "Slice14" SrcPort 1 Points [75, 0; 0, 10] DstBlock "Mux1" DstPort 13 } Line { SrcBlock "Slice15" SrcPort 1 Points [0, 20; 200, 0] DstBlock "Mux1" DstPort 14 } Line { SrcBlock "Slice16" SrcPort 1 Points [240, 0; 0, 10] DstBlock "Mux1" DstPort 15 } Line { SrcBlock "Slice17" SrcPort 1 Points [30, 0; 0, 15] DstBlock "Mux1" DstPort 16 } Line { SrcBlock "Slice18" SrcPort 1 Points [65, 0; 0, 15] DstBlock "Mux1" DstPort 17 } Line { SrcBlock "Slice19" SrcPort 1 Points [90, 0; 0, 15] DstBlock "Mux1" DstPort 18 } Line { SrcBlock "Slice12" SrcPort 1 Points [115, 0; 0, 10] DstBlock "Mux1" DstPort 19 } Line { SrcBlock "DA1_in" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [0, 25] Branch { Points [0, 35] Branch { Points [0, 30] Branch { Points [0, 5] DstBlock "Slice19" DstPort 1 } Branch { Points [0, 45] DstBlock "Slice12" DstPort 1 } } Branch { DstBlock "Slice18" DstPort 1 } } Branch { DstBlock "Slice17" DstPort 1 } } Branch { Points [0, -5] Branch { DstBlock "Slice16" DstPort 1 } Branch { Points [0, -40] Branch { DstBlock "Slice15" DstPort 1 } Branch { Points [0, -35] Branch { Points [0, -35] DstBlock "Slice11" DstPort 1 } Branch { Points [125, 0] DstBlock "Slice14" DstPort 1 } } } } } Line { SrcBlock "FSM counter" SrcPort 1 DstBlock "Slice2" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "DA0_out" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "DA1_out" DstPort 1 } } } Block { BlockType Outport Name "AD0_out" Position [775, 353, 805, 367] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "AD1_out" Position [810, 433, 840, 447] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "DA0_out" Position [805, 63, 835, 77] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "DA1_out" Position [725, 148, 755, 162] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "SYNC" Position [345, 228, 375, 242] Port "5" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "SCLK" Position [345, 278, 375, 292] Port "6" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "ADA Clock Generation" SrcPort 1 Points [35, 0; 0, -130] DstBlock "DA para2ser" DstPort 1 } Line { SrcBlock "ADA Clock Generation" SrcPort 4 DstBlock "AD ser2para" DstPort 1 } Line { SrcBlock "ADA Clock Generation" SrcPort 5 Points [200, 0] DstBlock "AD ser2para" DstPort 2 } Line { SrcBlock "DA para2ser" SrcPort 1 DstBlock "DA0_out" DstPort 1 } Line { SrcBlock "DA0_in" SrcPort 1 DstBlock "DA para2ser" DstPort 2 } Line { SrcBlock "DA para2ser" SrcPort 2 DstBlock "DA1_out" DstPort 1 } Line { SrcBlock "DA1_in" SrcPort 1 DstBlock "DA para2ser" DstPort 3 } Line { SrcBlock "ADA Clock Generation" SrcPort 2 DstBlock "SYNC" DstPort 1 } Line { SrcBlock "clk_reset" SrcPort 1 DstBlock "ADA Clock Generation" DstPort 1 } Line { SrcBlock "ADA Clock Generation" SrcPort 3 DstBlock "SCLK" DstPort 1 } Line { SrcBlock "AD ser2para" SrcPort 1 Points [0, 5] DstBlock "AD0_out" DstPort 1 } Line { SrcBlock "AD0_in" SrcPort 1 Points [145, 0] DstBlock "AD ser2para" DstPort 3 } Line { SrcBlock "AD ser2para" SrcPort 2 Points [0, -10] DstBlock "AD1_out" DstPort 1 } Line { SrcBlock "AD1_in" SrcPort 1 Points [145, 0] DstBlock "AD ser2para" DstPort 4 } } } Block { BlockType Reference Name "D0" Ports [1, 1] Position [1310, 684, 1365, 706] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "D1" Ports [1, 1] Position [1315, 734, 1370, 756] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [1050, 328, 1100, 362] SourceBlock "xbsIndex_r3/Inverter" SourceType "Xilinx Inverter" latency "0" explicit_period off period "1" en off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [1165, 408, 1210, 672] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "User Defined" arith_type "Unsigned" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[4 0 0 8 0 0 0]" xl_use_area off } Block { BlockType Step Name "Reset" Position [15, 680, 45, 710] Before "1" After "0" SampleTime "0" } Block { BlockType Step Name "Reset1" Position [15, 505, 45, 535] SampleTime "0" } Block { BlockType Step Name "Reset2" Position [15, 560, 45, 590] SampleTime "0" } Block { BlockType Reference Name "SCLK" Ports [1, 1] Position [1315, 944, 1370, 966] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "SYNC" Ports [1, 1] Position [1315, 844, 1370, 866] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Slice1" Ports [1, 1] Position [405, 296, 450, 324] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Lower Bit Location + Width" nbits "8" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "Slice2" Ports [1, 1] Position [405, 371, 450, 399] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "4" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "Slice3" Ports [1, 1] Position [385, 621, 430, 649] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Lower Bit Location + Width" nbits "8" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "Slice4" Ports [1, 1] Position [385, 681, 430, 709] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" boolean_output on explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "Slice5" Ports [1, 1] Position [1055, 436, 1100, 464] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Lower Bit Location + Width" nbits "1" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" boolean_output on explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "an" Ports [1, 1] Position [1315, 999, 1370, 1021] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0 0 0 0 8 0 0]" xl_use_area off } Block { BlockType Reference Name "bin2seven" Ports [1, 1] Position [550, 359, 600, 411] FontSize 10 SourceBlock "xbsIndex_r3/ROM" SourceType "Xilinx Single Port Read-Only Memory" depth "16" initVector "[63,6,91,79,102,109,125,7,127,111,119,124,57,94" ",121,113]" arith_type "Unsigned" n_bits "8" bin_pt "0" latency "2" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "btn" Ports [1, 1] Position [135, 684, 190, 706] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Unsigned" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0 0 0 0 8 0 0]" xl_use_area off } Block { BlockType Reference Name "coeffs " Ports [0, 1] Position [15, 295, 45, 325] SourceBlock "simulink/Sources/Repeating\nSequence" SourceType "Repeating table" ShowPortLabels on rep_seq_t "[1:20]" rep_seq_y "[0 10 10 10 10 10 10 10 10 0 0 0 0 0 0 0 0 0 0" " 0]" } Block { BlockType Reference Name "led" Ports [1, 1] Position [1300, 529, 1355, 551] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0 0 0 0 8 0 0]" xl_use_area off } Block { BlockType Reference Name "ssg" Ports [1, 1] Position [1295, 334, 1350, 356] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "swt" Ports [1, 1] Position [110, 299, 165, 321] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Signed (2's comp)" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } } } MatData { NumRecords 1 DataRecord { Tag DataTag0 Data " %)30 . \\ @ 8 ( @ % " "\" $ ! 0 % 0 !@ $ & 7, !V86QU97, . < 8 ( 0 % \" $ ! " " 0 . 0 8 ( ! % \" $ + 0 " "0 \"P $A$3\"!.971L:7-T . : 8 ( 0 % \" " " $ ! 0 . . 8 ( ! % \" $ ' " "0 0 !P '1A7-T96T #@ $@ & \" " " 0 !0 @ ! & $ $ !@ !!8V-O0 !T97-T8F5N8V@ 6YT:&5S:7-?;&%N9W5A9V4 X X !@" " @ $ 4 ( 0 @ ! ! ( 4W!A 8 ( ! % \" $ !$ 0 " " 0 1 $,Z+T1O8W5M96YT