Model { Name "Lab8" Version 6.1 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.63" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "ibm-5348_P100-1997" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Wed Nov 15 23:04:18 2006" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "umb" ModifiedDateFormat "%" LastModifiedDate "Fri Apr 06 09:54:39 2007" ModelVersionFormat "1.%" ConfigurationManager "None" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on StrictBusMsg "None" ProdHWDeviceType "32-bit Generic" ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.0.4" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.0.4" StartTime "0.0" StopTime "20" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" RelTol "1e-3" SolverMode "SingleTasking" Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" ZeroCrossControl "UseLocalSettings" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" RateTranMode "Deterministic" } Simulink.DataIOCC { $ObjectID 3 Version "1.0.4" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.0.4" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on ConditionalExecOptimization "on_for_testing" InlineParams off InlineInvariantSignals on OptimizeBlockIOStorage on BufferReuse on EnforceIntegerDowncast on ExpressionFolding on FoldNonRolledExpr on LocalBlockOutputs on ParameterPooling on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off OptimizeModelRefInitCode off LifeSpan "inf" } Simulink.DebuggingCC { $ObjectID 5 Version "1.0.4" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.0.4" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.0.4" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.0.4" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 9 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" PropName "DisabledProps" } Version "1.0.4" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off PrefixModelToSubsysFcnNames on CustomSymbolStr "$R$N$M" MangleLength 1 DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 12 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" PropName "DisabledProps" } Version "1.0.4" TargetFcnLib "ansi_tfl_tmw.mat" GenFloatMathFcnCalls "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off IsPILTarget off ModelReferenceCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" SimulationMode "normal" CurrentDlgPage "Solver" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Clock DisplayTime off } Block { BlockType Constant Value "1" VectorParams1D on OutDataTypeMode "Inherit from 'Constant value'" OutDataType "sfix(16)" ConRadixGroup "Use specified scaling" OutScaling "2^0" SampleTime "inf" } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Fcn Expr "sin(u[1])" SampleTime "-1" } Block { BlockType SignalConversion OverrideOpt off } Block { BlockType Inport BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Lookup InputValues "[-4:5]" OutputValues " rand(1,10)-0.5" LookUpMeth "Interpolation-Extrapolation" OutDataTypeMode "Same as input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" LUTDesignTableMode "Redesign Table" LUTDesignDataSource "Block Dialog" LUTDesignFunctionName "sqrt(x)" LUTDesignUseExistingBP on LUTDesignRelError "0.01" LUTDesignAbsError "1e-6" } Block { BlockType Outport Port "1" BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Reference } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType "S-Function" FunctionName "system" SFunctionModules "''" PortCounts "[]" } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" PermitHierarchicalResolution "All" SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Terminator } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "Lab8" Location [52, 91, 984, 677] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "73" ReportName "simulink-default.rpt" Block { BlockType Reference Name " System Generator" Tag "genX" Ports [] Position [92, 43, 143, 93] ShowName off AttributesFormatString "System\\nGenerator" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r3/ System Generator" SourceType "Xilinx System Generator" ShowPortLabels on xilinxfamily "Spartan3" part "xc3s200" speed "-5" package "ft256" synthesis_tool "XST" directory "C:/xup/fft" testbench off simulink_period "1" sysclk_period "100" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [1085, 115, 1115, 145] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay1" Ports [1, 1] Position [1085, 155, 1115, 185] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay10" Ports [1, 1] Position [1090, 540, 1120, 570] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay11" Ports [1, 1] Position [1090, 580, 1120, 610] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay12" Ports [1, 1] Position [1090, 620, 1120, 650] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay13" Ports [1, 1] Position [1090, 660, 1120, 690] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay14" Ports [1, 1] Position [1090, 700, 1120, 730] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay15" Ports [1, 1] Position [1090, 740, 1120, 770] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay2" Ports [1, 1] Position [1090, 195, 1120, 225] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay3" Ports [1, 1] Position [1090, 235, 1120, 265] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay4" Ports [1, 1] Position [1090, 275, 1120, 305] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay5" Ports [1, 1] Position [1090, 315, 1120, 345] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay6" Ports [1, 1] Position [1090, 355, 1120, 385] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay7" Ports [1, 1] Position [1090, 395, 1120, 425] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay8" Ports [1, 1] Position [1095, 460, 1120, 490] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay9" Ports [1, 1] Position [1090, 500, 1120, 530] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Scope Name "Imag Scope" Ports [8] Position [1225, 459, 1265, 771] Location [5, 49, 1029, 745] Open off NumInputPorts "8" List { ListType AxesTitles axes1 "X[0]" axes2 "X[1]" axes3 "X[2]" axes4 "X[3]" axes5 "X[4]" axes6 "X[5]" axes7 "X[6]" axes8 "X[7]" } YMin "-22~-22~-22~-22~-22~-22~-22~-22" YMax "22~22~22~22~22~22~22~22" SaveName "ScopeData1" DataFormat "StructureWithTime" } Block { BlockType Reference Name "Input Enable" Ports [1, 1] Position [105, 369, 160, 391] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Boolean" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Input Im" Ports [1, 1] Position [105, 549, 160, 571] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Signed (2's comp)" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Input Re" Ports [1, 1] Position [105, 234, 160, 256] SourceBlock "xbsIndex_r3/Gateway In" SourceType "Xilinx Gateway In" arith_type "Unsigned" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xim0" Ports [1, 1] Position [1140, 464, 1195, 486] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xim1" Ports [1, 1] Position [1140, 504, 1195, 526] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xim2" Ports [1, 1] Position [1140, 544, 1195, 566] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xim3" Ports [1, 1] Position [1140, 584, 1195, 606] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xim4" Ports [1, 1] Position [1140, 624, 1195, 646] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xim5" Ports [1, 1] Position [1140, 664, 1195, 686] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xim6" Ports [1, 1] Position [1140, 704, 1195, 726] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xim7" Ports [1, 1] Position [1140, 744, 1195, 766] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xre0" Ports [1, 1] Position [1140, 119, 1195, 141] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xre1" Ports [1, 1] Position [1140, 159, 1195, 181] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xre2" Ports [1, 1] Position [1140, 199, 1195, 221] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xre3" Ports [1, 1] Position [1140, 239, 1195, 261] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xre4" Ports [1, 1] Position [1140, 279, 1195, 301] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xre5" Ports [1, 1] Position [1140, 319, 1195, 341] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xre6" Ports [1, 1] Position [1140, 359, 1195, 381] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Output Xre7" Ports [1, 1] Position [1140, 399, 1195, 421] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator" Ports [0, 1] Position [40, 363, 85, 397] Period "100" PulseWidth "8" PhaseDelay "1" } Block { BlockType Scope Name "Real Scope" Ports [8] Position [1225, 109, 1265, 431] Location [5, 49, 1029, 745] Open off NumInputPorts "8" List { ListType AxesTitles axes1 "X[0]" axes2 "X[1]" axes3 "X[2]" axes4 "X[3]" axes5 "X[4]" axes6 "X[5]" axes7 "X[6]" axes8 "X[7]" } YMin "0~-12~-12~-12~-12~-12~-12~-12" YMax "100~12~12~12~12~12~12~12" SaveName "ScopeData2" DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope W1" Ports [4] Position [630, 43, 660, 182] Location [1, 43, 1025, 739] Open off NumInputPorts "4" List { ListType AxesTitles axes1 "Dre" axes2 "Dim" axes3 "Ere" axes4 "Eim" } YMin "-5~-5~-5~-5" YMax "5~5~5~5" SaveName "ScopeData3" DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope W3" Ports [4] Position [635, 652, 670, 803] Location [5, 47, 1029, 743] Open off NumInputPorts "4" List { ListType AxesTitles axes1 "Dre" axes2 "Dim" axes3 "Ere" axes4 "Eim" } YMin "-5~-5~-5~-5" YMax "5~5~5~5" DataFormat "StructureWithTime" } Block { BlockType Reference Name "Scope1" Ports [1, 1] Position [545, 49, 600, 71] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Scope2" Ports [1, 1] Position [545, 84, 600, 106] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Scope3" Ports [1, 1] Position [545, 119, 600, 141] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Scope4" Ports [1, 1] Position [545, 154, 600, 176] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Scope5" Ports [1, 1] Position [545, 664, 600, 686] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Scope6" Ports [1, 1] Position [545, 699, 600, 721] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Scope7" Ports [1, 1] Position [545, 734, 600, 756] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Scope8" Ports [1, 1] Position [545, 769, 600, 791] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port off timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType SubSystem Name "Shift Taps Real" Ports [2, 8] Position [205, 175, 255, 450] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "Shift Taps Real" Location [2, 74, 1014, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "d" Position [165, 93, 195, 107] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "enable" Position [165, 118, 195, 132] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Delay0" Ports [2, 1] Position [310, 154, 355, 201] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay1" Ports [2, 1] Position [310, 219, 355, 266] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "3" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay2" Ports [2, 1] Position [310, 284, 355, 331] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "4" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay3" Ports [2, 1] Position [310, 349, 355, 396] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "5" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay4" Ports [2, 1] Position [310, 414, 355, 461] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "6" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay5" Ports [2, 1] Position [310, 479, 355, 526] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "7" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay6" Ports [2, 1] Position [310, 544, 355, 591] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "8" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay7" Ports [2, 1] Position [310, 89, 355, 136] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Outport Name "t0" Position [405, 108, 435, 122] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t1" Position [405, 173, 435, 187] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t2" Position [405, 238, 435, 252] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t3" Position [405, 303, 435, 317] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t4" Position [405, 368, 435, 382] Port "5" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t5" Position [405, 433, 435, 447] Port "6" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t6" Position [405, 498, 435, 512] Port "7" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t7" Position [405, 563, 435, 577] Port "8" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "d" SrcPort 1 Points [60, 0] Branch { Points [0, 65] Branch { DstBlock "Delay0" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay1" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay4" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay5" DstPort 1 } Branch { Points [0, 65] DstBlock "Delay6" DstPort 1 } } } } } } } Branch { DstBlock "Delay7" DstPort 1 } } Line { SrcBlock "Delay0" SrcPort 1 DstBlock "t1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "t2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "t3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "t4" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "t5" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "t6" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "t7" DstPort 1 } Line { SrcBlock "enable" SrcPort 1 Points [20, 0] Branch { Points [0, 65] Branch { Points [0, 0] DstBlock "Delay0" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay1" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay2" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay3" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay4" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay5" DstPort 2 } Branch { Points [0, 65] DstBlock "Delay6" DstPort 2 } } } } } } } Branch { DstBlock "Delay7" DstPort 2 } } Line { SrcBlock "Delay7" SrcPort 1 DstBlock "t0" DstPort 1 } } } Block { BlockType SubSystem Name "Shift Taps Real1" Ports [2, 8] Position [205, 499, 255, 741] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "Shift Taps Real1" Location [2, 74, 1014, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "d" Position [165, 93, 195, 107] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "enable" Position [165, 118, 195, 132] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Delay0" Ports [2, 1] Position [310, 154, 355, 201] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay1" Ports [2, 1] Position [310, 219, 355, 266] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "3" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay2" Ports [2, 1] Position [310, 284, 355, 331] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "4" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay3" Ports [2, 1] Position [310, 349, 355, 396] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "5" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay4" Ports [2, 1] Position [310, 414, 355, 461] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "6" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay5" Ports [2, 1] Position [310, 479, 355, 526] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "7" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay6" Ports [2, 1] Position [310, 544, 355, 591] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "8" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Delay7" Ports [2, 1] Position [310, 89, 355, 136] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming "off" explicit_period "off" period "1" en "on" accept_only_valid "off" init_zero "on" dbl_ovrd "off" show_param "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Outport Name "t0" Position [380, 108, 410, 122] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t1" Position [380, 173, 410, 187] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t2" Position [380, 238, 410, 252] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t3" Position [380, 303, 410, 317] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t4" Position [380, 368, 410, 382] Port "5" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t5" Position [380, 433, 410, 447] Port "6" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t6" Position [380, 498, 410, 512] Port "7" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "t7" Position [380, 563, 410, 577] Port "8" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "d" SrcPort 1 Points [60, 0] Branch { Points [0, 65] Branch { DstBlock "Delay0" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay1" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay4" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Delay5" DstPort 1 } Branch { Points [0, 65] DstBlock "Delay6" DstPort 1 } } } } } } } Branch { DstBlock "Delay7" DstPort 1 } } Line { SrcBlock "Delay0" SrcPort 1 DstBlock "t1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "t2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "t3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "t4" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "t5" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "t6" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "t7" DstPort 1 } Line { SrcBlock "enable" SrcPort 1 Points [20, 0] Branch { Points [0, 65] Branch { Points [0, 0] DstBlock "Delay0" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay1" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay2" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay3" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay4" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Delay5" DstPort 2 } Branch { Points [0, 65] DstBlock "Delay6" DstPort 2 } } } } } } } Branch { DstBlock "Delay7" DstPort 2 } } Line { SrcBlock "Delay7" SrcPort 1 DstBlock "t0" DstPort 1 } } } Block { BlockType SubSystem Name "W0 Butterfly 1. stage1" Ports [4, 4] Position [390, 185, 485, 265] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "W0 Butterfly 1. stage1" Location [2, 74, 1012, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "Are" Position [105, 98, 135, 112] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Aim" Position [105, 178, 135, 192] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bre" Position [105, 283, 135, 297] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bim" Position [105, 358, 135, 372] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Aim minus Bim" Ports [2, 1] Position [370, 327, 420, 378] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Subtraction" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period "off" period "1" use_carryin "off" use_carryout "off" en "off" dbl_ovrd "off" show_param "off" use_core "on" pipeline "off" use_rpm "on" gen_core "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Aim plus Bim" Ports [2, 1] Position [370, 172, 420, 223] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period "off" period "1" use_carryin "off" use_carryout "off" en "off" dbl_ovrd "off" show_param "off" use_core "on" pipeline "off" use_rpm "on" gen_core "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Are minus Bre" Ports [2, 1] Position [370, 252, 420, 303] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Subtraction" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period "off" period "1" use_carryin "off" use_carryout "off" en "off" dbl_ovrd "off" show_param "off" use_core "on" pipeline "off" use_rpm "on" gen_core "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Are plus Bre" Ports [2, 1] Position [370, 92, 420, 143] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period "off" period "1" use_carryin "off" use_carryout "off" en "off" dbl_ovrd "off" show_param "off" use_core "on" pipeline "off" use_rpm "on" gen_core "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Outport Name "Dre" Position [560, 113, 590, 127] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Dim" Position [560, 193, 590, 207] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Ere" Position [560, 273, 590, 287] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Eim" Position [560, 348, 590, 362] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "Are" SrcPort 1 Points [100, 0; 10, 0] Branch { Points [0, 160] DstBlock "Are minus Bre" DstPort 1 } Branch { DstBlock "Are plus Bre" DstPort 1 } } Line { SrcBlock "Bre" SrcPort 1 Points [150, 0] Branch { DstBlock "Are minus Bre" DstPort 2 } Branch { Points [0, -160] DstBlock "Are plus Bre" DstPort 2 } } Line { SrcBlock "Aim" SrcPort 1 Points [55, 0; 15, 0] Branch { DstBlock "Aim plus Bim" DstPort 1 } Branch { Points [0, 155] DstBlock "Aim minus Bim" DstPort 1 } } Line { SrcBlock "Are plus Bre" SrcPort 1 DstBlock "Dre" DstPort 1 } Line { SrcBlock "Aim plus Bim" SrcPort 1 DstBlock "Dim" DstPort 1 } Line { SrcBlock "Bim" SrcPort 1 Points [185, 0] Branch { Points [0, -155] DstBlock "Aim plus Bim" DstPort 2 } Branch { DstBlock "Aim minus Bim" DstPort 2 } } Line { SrcBlock "Are minus Bre" SrcPort 1 DstBlock "Ere" DstPort 1 } Line { SrcBlock "Aim minus Bim" SrcPort 1 DstBlock "Eim" DstPort 1 } Annotation { Name "Complex butterfly for w^0=1." Position [399, 26] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } Block { BlockType SubSystem Name "W1 Butterfly 1. stage1" Ports [4, 4] Position [390, 310, 485, 390] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "W1 Butterfly 1. stage1" Location [2, 74, 1014, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "Are" Position [105, 68, 135, 82] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Aim" Position [105, 178, 135, 192] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bre" Position [105, 308, 135, 322] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bim" Position [105, 413, 135, 427] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Outport Name "Dre" Position [865, 83, 895, 97] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Dim" Position [865, 193, 895, 207] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Ere" Position [865, 388, 895, 402] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Eim" Position [865, 508, 895, 522] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Annotation { Name "Complex butterfly for w^1=exp(-j*\\pi/4)." Position [404, 26] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } Block { BlockType SubSystem Name "W2 Butterfly 1. stage1" Ports [4, 4] Position [390, 440, 485, 520] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "W2 Butterfly 1. stage1" Location [2, 74, 1014, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "Are" Position [105, 58, 135, 72] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Aim" Position [105, 178, 135, 192] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bre" Position [105, 328, 135, 342] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bim" Position [105, 448, 135, 462] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Aim plus Bim" Ports [2, 1] Position [370, 172, 420, 223] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period "off" period "1" use_carryin "off" use_carryout "off" en "off" dbl_ovrd "off" show_param "off" use_core "on" pipeline "off" use_rpm "on" gen_core "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Are plus Bre" Ports [2, 1] Position [370, 52, 420, 103] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Addition" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period "off" period "1" use_carryin "off" use_carryout "off" en "off" dbl_ovrd "off" show_param "off" use_core "on" pipeline "off" use_rpm "on" gen_core "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Bim minus Aim" Ports [2, 1] Position [370, 417, 420, 468] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Subtraction" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period "off" period "1" use_carryin "off" use_carryout "off" en "off" dbl_ovrd "off" show_param "off" use_core "on" pipeline "off" use_rpm "on" gen_core "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Reference Name "Bre minus Are" Ports [2, 1] Position [370, 297, 420, 348] SourceBlock "xbsIndex_r3/AddSub" SourceType "Xilinx Adder/Subtractor" mode "Subtraction" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "0" explicit_period "off" period "1" use_carryin "off" use_carryout "off" en "off" dbl_ovrd "off" show_param "off" use_core "on" pipeline "off" use_rpm "on" gen_core "off" xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area "off" } Block { BlockType Outport Name "Dre" Position [560, 73, 590, 87] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Dim" Position [560, 193, 590, 207] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Ere" Position [560, 318, 590, 332] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Eim" Position [560, 423, 590, 437] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "Are" SrcPort 1 Points [100, 0; 10, 0] Branch { DstBlock "Are plus Bre" DstPort 1 } Branch { Points [0, 230; 105, 0] DstBlock "Bre minus Are" DstPort 2 } } Line { SrcBlock "Bre" SrcPort 1 Points [0, 0; 150, 0] Branch { Points [0, -245] DstBlock "Are plus Bre" DstPort 2 } Branch { Points [45, 0; 0, -25] DstBlock "Bre minus Are" DstPort 1 } } Line { SrcBlock "Aim" SrcPort 1 Points [55, 0; 15, 0] Branch { DstBlock "Aim plus Bim" DstPort 1 } Branch { Points [0, 225; 145, 0] DstBlock "Bim minus Aim" DstPort 2 } } Line { SrcBlock "Are plus Bre" SrcPort 1 DstBlock "Dre" DstPort 1 } Line { SrcBlock "Aim plus Bim" SrcPort 1 DstBlock "Dim" DstPort 1 } Line { SrcBlock "Bim" SrcPort 1 Points [0, 0; 185, 0] Branch { Points [0, -245] DstBlock "Aim plus Bim" DstPort 2 } Branch { Points [20, 0; 0, -25] DstBlock "Bim minus Aim" DstPort 1 } } Line { SrcBlock "Bre minus Are" SrcPort 1 Points [55, 0; 0, 105] DstBlock "Eim" DstPort 1 } Line { SrcBlock "Bim minus Aim" SrcPort 1 Points [75, 0; 0, -120] DstBlock "Ere" DstPort 1 } Annotation { Name "Complex butterfly for w^2=-j." Position [409, 26] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } Block { BlockType SubSystem Name "W3 Butterfly 1. stage1" Ports [4, 4] Position [390, 565, 485, 645] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "W3 Butterfly 1. stage1" Location [2, 74, 1014, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "Are" Position [105, 68, 135, 82] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Aim" Position [105, 178, 135, 192] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bre" Position [105, 308, 135, 322] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bim" Position [105, 413, 135, 427] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Outport Name "Dre" Position [775, 83, 805, 97] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Dim" Position [775, 193, 805, 207] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Ere" Position [780, 388, 810, 402] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Eim" Position [780, 508, 810, 522] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Annotation { Name "Complex butterfly for w^3=exp(-j*3*\\pi/4)." Position [389, 26] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } Block { BlockType Constant Name "x Imag is zero" Position [50, 545, 80, 575] Value "0" } Block { BlockType Reference Name "x Real has \ntriangular" Ports [0, 1] Position [50, 230, 80, 260] SourceBlock "simulink/Sources/Repeating\nSequence" SourceType "Repeating table" ShowPortLabels on rep_seq_t "[0 1 2 3 4 5 6 7 8 9 10 100]" rep_seq_y "[0 16 14 12 10 8 6 4 2 0 0 0]" } Line { SrcBlock "W3 Butterfly 1. stage1" SrcPort 3 Points [10, 0; 0, 130] DstBlock "Scope7" DstPort 1 } Line { SrcBlock "W3 Butterfly 1. stage1" SrcPort 4 Points [5, 0; 0, 145] DstBlock "Scope8" DstPort 1 } Line { SrcBlock "W1 Butterfly 1. stage1" SrcPort 4 Points [20, 0; 0, -215] DstBlock "Scope4" DstPort 1 } Line { SrcBlock "W1 Butterfly 1. stage1" SrcPort 3 Points [15, 0; 0, -230] DstBlock "Scope3" DstPort 1 } Line { SrcBlock "W3 Butterfly 1. stage1" SrcPort 1 Points [20, 0; 0, 100] DstBlock "Scope5" DstPort 1 } Line { SrcBlock "W3 Butterfly 1. stage1" SrcPort 2 Points [15, 0; 0, 115] DstBlock "Scope6" DstPort 1 } Line { SrcBlock "W1 Butterfly 1. stage1" SrcPort 1 Points [5, 0; 0, -260] DstBlock "Scope1" DstPort 1 } Line { SrcBlock "W1 Butterfly 1. stage1" SrcPort 2 Points [10, 0; 0, -245] DstBlock "Scope2" DstPort 1 } Line { SrcBlock "Output Xre0" SrcPort 1 DstBlock "Real Scope" DstPort 1 } Line { SrcBlock "Output Xre1" SrcPort 1 DstBlock "Real Scope" DstPort 2 } Line { SrcBlock "Output Xre2" SrcPort 1 DstBlock "Real Scope" DstPort 3 } Line { SrcBlock "Output Xre3" SrcPort 1 DstBlock "Real Scope" DstPort 4 } Line { SrcBlock "Output Xre4" SrcPort 1 DstBlock "Real Scope" DstPort 5 } Line { SrcBlock "Output Xre5" SrcPort 1 DstBlock "Real Scope" DstPort 6 } Line { SrcBlock "Output Xre6" SrcPort 1 DstBlock "Real Scope" DstPort 7 } Line { SrcBlock "Output Xre7" SrcPort 1 DstBlock "Real Scope" DstPort 8 } Line { SrcBlock "Output Xim0" SrcPort 1 DstBlock "Imag Scope" DstPort 1 } Line { SrcBlock "Output Xim1" SrcPort 1 DstBlock "Imag Scope" DstPort 2 } Line { SrcBlock "Output Xim2" SrcPort 1 DstBlock "Imag Scope" DstPort 3 } Line { SrcBlock "Output Xim3" SrcPort 1 DstBlock "Imag Scope" DstPort 4 } Line { SrcBlock "Output Xim4" SrcPort 1 DstBlock "Imag Scope" DstPort 5 } Line { SrcBlock "Output Xim5" SrcPort 1 DstBlock "Imag Scope" DstPort 6 } Line { SrcBlock "Output Xim6" SrcPort 1 DstBlock "Imag Scope" DstPort 7 } Line { SrcBlock "Output Xim7" SrcPort 1 DstBlock "Imag Scope" DstPort 8 } Line { SrcBlock "Shift Taps Real" SrcPort 1 Points [55, 0; 0, 5] DstBlock "W0 Butterfly 1. stage1" DstPort 1 } Line { SrcBlock "Shift Taps Real" SrcPort 2 Points [110, 0; 0, 95] DstBlock "W1 Butterfly 1. stage1" DstPort 1 } Line { SrcBlock "Shift Taps Real" SrcPort 3 Points [100, 0; 0, 190] DstBlock "W2 Butterfly 1. stage1" DstPort 1 } Line { SrcBlock "Shift Taps Real" SrcPort 4 Points [45, 0; 0, 280] DstBlock "W3 Butterfly 1. stage1" DstPort 1 } Line { SrcBlock "Shift Taps Real" SrcPort 5 Points [70, 0; 0, -95] DstBlock "W0 Butterfly 1. stage1" DstPort 3 } Line { SrcBlock "Shift Taps Real" SrcPort 6 Points [115, 0] DstBlock "W1 Butterfly 1. stage1" DstPort 3 } Line { SrcBlock "Shift Taps Real" SrcPort 7 Points [110, 0; 0, 90] DstBlock "W2 Butterfly 1. stage1" DstPort 3 } Line { SrcBlock "Shift Taps Real" SrcPort 8 Points [35, 0; 0, 180] DstBlock "W3 Butterfly 1. stage1" DstPort 3 } Line { SrcBlock "Shift Taps Real1" SrcPort 1 Points [75, 0; 0, -300] DstBlock "W0 Butterfly 1. stage1" DstPort 2 } Line { SrcBlock "Shift Taps Real1" SrcPort 2 Points [90, 0; 0, -205] DstBlock "W1 Butterfly 1. stage1" DstPort 2 } Line { SrcBlock "Shift Taps Real1" SrcPort 3 Points [15, 0; 0, -105] DstBlock "W2 Butterfly 1. stage1" DstPort 2 } Line { SrcBlock "Shift Taps Real1" SrcPort 4 Points [75, 0; 0, -10] DstBlock "W3 Butterfly 1. stage1" DstPort 2 } Line { SrcBlock "Shift Taps Real1" SrcPort 5 Points [25, 0; 0, -380] DstBlock "W0 Butterfly 1. stage1" DstPort 4 } Line { SrcBlock "Shift Taps Real1" SrcPort 6 Points [55, 0; 0, -285] DstBlock "W1 Butterfly 1. stage1" DstPort 4 } Line { SrcBlock "Shift Taps Real1" SrcPort 7 Points [110, 0; 0, -185] DstBlock "W2 Butterfly 1. stage1" DstPort 4 } Line { SrcBlock "Shift Taps Real1" SrcPort 8 Points [115, 0] DstBlock "W3 Butterfly 1. stage1" DstPort 4 } Line { SrcBlock "Scope1" SrcPort 1 DstBlock "Scope W1" DstPort 1 } Line { SrcBlock "Scope2" SrcPort 1 DstBlock "Scope W1" DstPort 2 } Line { SrcBlock "Scope3" SrcPort 1 DstBlock "Scope W1" DstPort 3 } Line { SrcBlock "Scope4" SrcPort 1 DstBlock "Scope W1" DstPort 4 } Line { SrcBlock "Scope5" SrcPort 1 DstBlock "Scope W3" DstPort 1 } Line { SrcBlock "Scope6" SrcPort 1 DstBlock "Scope W3" DstPort 2 } Line { SrcBlock "Scope7" SrcPort 1 DstBlock "Scope W3" DstPort 3 } Line { SrcBlock "Scope8" SrcPort 1 DstBlock "Scope W3" DstPort 4 } Line { SrcBlock "Input Enable" SrcPort 1 Points [5, 0; 15, 0] Branch { Points [0, 300] DstBlock "Shift Taps Real1" DstPort 2 } Branch { DstBlock "Shift Taps Real" DstPort 2 } } Line { SrcBlock "x Imag is zero" SrcPort 1 DstBlock "Input Im" DstPort 1 } Line { SrcBlock "Input Im" SrcPort 1 DstBlock "Shift Taps Real1" DstPort 1 } Line { SrcBlock "Pulse\nGenerator" SrcPort 1 DstBlock "Input Enable" DstPort 1 } Line { SrcBlock "Input Re" SrcPort 1 DstBlock "Shift Taps Real" DstPort 1 } Line { SrcBlock "x Real has \ntriangular" SrcPort 1 DstBlock "Input Re" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Output Xre0" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Output Xre1" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Output Xre2" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Output Xre3" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Output Xre4" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Output Xre5" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Output Xre6" DstPort 1 } Line { SrcBlock "Delay7" SrcPort 1 DstBlock "Output Xre7" DstPort 1 } Line { SrcBlock "Delay8" SrcPort 1 DstBlock "Output Xim0" DstPort 1 } Line { SrcBlock "Delay9" SrcPort 1 DstBlock "Output Xim1" DstPort 1 } Line { SrcBlock "Delay10" SrcPort 1 DstBlock "Output Xim2" DstPort 1 } Line { SrcBlock "Delay11" SrcPort 1 DstBlock "Output Xim3" DstPort 1 } Line { SrcBlock "Delay15" SrcPort 1 DstBlock "Output Xim7" DstPort 1 } Line { SrcBlock "Delay14" SrcPort 1 DstBlock "Output Xim6" DstPort 1 } Line { SrcBlock "Delay13" SrcPort 1 DstBlock "Output Xim5" DstPort 1 } Line { SrcBlock "Delay12" SrcPort 1 DstBlock "Output Xim4" DstPort 1 } Annotation { Position [5, 556] } Annotation { Name "1. stage" Position [434, 151] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } Annotation { Name "2. stage" Position [744, 151] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } Annotation { Name "3. stage" Position [959, 151] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } MatData { NumRecords 1 DataRecord { Tag DataTag0 Data " %)30 . .!$ 8 ( @ % " "\" $ ! 0 % 0 !@ $ , 7=H97)E(&EN(%-U8E-Y&9A;6EL>0 !P87)T" " 6YT:" "&5S:7-?=&]O; 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