Model { Name "sfg" Version 6.1 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.57" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "ibm-5348_P100-1997" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Tue Jun 21 08:08:39 2005" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "nobody" ModifiedDateFormat "%" LastModifiedDate "Wed Dec 07 18:45:38 2005" ModelVersionFormat "1.%" ConfigurationManager "None" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on StrictBusMsg "None" ProdHWDeviceType "32-bit Generic" ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.0.4" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.0.4" StartTime "0.0" StopTime "20" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" RelTol "1e-3" SolverMode "SingleTasking" Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" ZeroCrossControl "UseLocalSettings" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" RateTranMode "Deterministic" } Simulink.DataIOCC { $ObjectID 3 Version "1.0.4" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.0.4" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on ConditionalExecOptimization "on_for_testing" InlineParams off InlineInvariantSignals on OptimizeBlockIOStorage on BufferReuse on EnforceIntegerDowncast on ExpressionFolding on FoldNonRolledExpr on LocalBlockOutputs on ParameterPooling on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off OptimizeModelRefInitCode off LifeSpan "inf" } Simulink.DebuggingCC { $ObjectID 5 Version "1.0.4" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" SolverPrmCheckMsg "none" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.0.4" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.0.4" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.0.4" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 9 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" PropName "DisabledProps" } Version "1.0.4" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off PrefixModelToSubsysFcnNames on CustomSymbolStr "$R$N$M" MangleLength 1 DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 12 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" PropName "DisabledProps" } Version "1.0.4" TargetFcnLib "ansi_tfl_tmw.mat" GenFloatMathFcnCalls "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off IsPILTarget off ModelReferenceCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" SimulationMode "normal" CurrentDlgPage "Solver" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 14 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Clock DisplayTime off } Block { BlockType Fcn Expr "sin(u[1])" SampleTime "-1" } Block { BlockType SignalConversion OverrideOpt off } Block { BlockType Lookup InputValues "[-4:5]" OutputValues " rand(1,10)-0.5" LookUpMeth "Interpolation-Extrapolation" OutDataTypeMode "Same as input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" LUTDesignTableMode "Redesign Table" LUTDesignDataSource "Block Dialog" LUTDesignFunctionName "sqrt(x)" LUTDesignUseExistingBP on LUTDesignRelError "0.01" LUTDesignAbsError "1e-6" } Block { BlockType Outport Port "1" BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType "S-Function" FunctionName "system" SFunctionModules "''" PortCounts "[]" } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" PermitHierarchicalResolution "All" SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType UnitDelay X0 "0" SampleTime "1" StateMustResolveToSignalObject off RTWStateStorageClass "Auto" } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 14 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 14 FontWeight "normal" FontAngle "normal" } System { Name "sfg" Location [2, 78, 1150, 814] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "88" ReportName "simulink-default.rpt" Block { BlockType Reference Name "Input" Description "Sign Binary Fractionnal" Ports [1, 1] Position [145, 97, 210, 113] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input" ppat "C:\\Documents and Settings\\Estrella\\labSFGdoc" "\\DSPBuilder_blacksystembox" nSgCpl "1" Port { PortNumber 1 Name "Impulse input" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType Reference Name "Output 2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [615, 332, 680, 348] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" Port { PortNumber 1 Name "system 2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType Reference Name "Output 3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [620, 507, 685, 523] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" Port { PortNumber 1 Name "system 3" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType Reference Name "Output1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [605, 167, 670, 183] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" Port { PortNumber 1 Name "system 1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" ShowSigGenPortName on } } Block { BlockType Scope Name "Scope" Ports [4] Position [780, 36, 875, 554] Location [410, 67, 997, 708] Open off NumInputPorts "4" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" } YMin "-22~-42~-5~-22" YMax "12~22~22~15" DataFormat "StructureWithTime" } Block { BlockType Reference Name "SignalCompiler" Ports [] Position [64, 188, 133, 235] ForegroundColor "blue" FontSize 10 SourceBlock "ALTELINK/AltLab/SignalCompiler" SourceType "SignalCompiler" family "DSP Board" opt "Speed" synthtool "Others" vstim on SynthAct "None" workdir "C:\\Documents and Settings\\Estrella\\labSFGdoc" Procetype "prod" UseReset on ResetPin "Active High" ClockPin "Output to Pin" ClockPeriod "20" UseSignalTap off CreatePtfFile off SignalTapDepth "128" VerilogSupport off UniqueVHDLHierarchyName off RegenerateIPFunctionalModel off RunUpdatedSimulation off JTAGCable "USB-Blaster [USB-0]" } Block { BlockType Reference Name "Stratix DSP Board 1S25\nConfiguration" Ports [] Position [68, 281, 133, 340] SourceBlock "dspboard1S25_alteradspbuilder/Stratix DSP Board" " 1S25\nConfiguration" SourceType "DspBoard AlteraBlockSet" DspBoard "dspboard1S25" family "STRATIX" ClockPinIn "Pin_K17" Clock1PinOut "None" Clock2PinOut "None" ClockPinOut "None" GlobalResetPin "Any" Device "EP1S25F780C5" JTAGDevice "@1: EP1S25F1020/780 (0x020030DD)" } Block { BlockType UnitDelay Name "Unit Delay" Position [85, 87, 115, 123] } Block { BlockType Reference Name "x_in" Ports [0, 1] Position [25, 90, 55, 120] SourceBlock "simulink/Sources/Repeating\nSequence" SourceType "Repeating table" ShowPortLabels on rep_seq_t "[1:20]" rep_seq_y "[10 0 0 0 0 0 0 0 0 0 0 -20 0 0 0 0 0 0 0 0]" } Line { Name "system 2" Labels [0, 0] SrcBlock "Output 2" SrcPort 1 Points [80, 0] DstBlock "Scope" DstPort 3 } Line { SrcBlock "x_in" SrcPort 1 DstBlock "Unit Delay" DstPort 1 } Line { Name "Impulse input" Labels [0, 0] SrcBlock "Input" SrcPort 1 Points [20, 0] Branch { Points [0, 230] Branch { Points [60, 0] } Branch { Points [0, 185; 55, 0] } } Branch { Points [0, -5] Branch { Labels [2, 0] Points [0, -75; 490, 0; 0, 75] DstBlock "Scope" DstPort 1 } Branch { Points [0, 80; 60, 0] } } } Line { SrcBlock "Unit Delay" SrcPort 1 DstBlock "Input" DstPort 1 } Line { Name "system 1" Labels [1, 0] SrcBlock "Output1" SrcPort 1 Points [45, 0; 0, 55] DstBlock "Scope" DstPort 2 } Line { Name "system 3" Labels [0, 0] SrcBlock "Output 3" SrcPort 1 Points [75, 0] DstBlock "Scope" DstPort 4 } Line { Labels [0, 0] Points [550, 175] DstBlock "Output1" DstPort 1 } Line { Labels [0, 0] Points [555, 340] DstBlock "Output 2" DstPort 1 } Line { Points [555, 515] DstBlock "Output 3" DstPort 1 } } }