Model {
  Name			  "goertzel8"
  Version		  6.1
  MdlSubVersion		  0
  GraphicalInterface {
    NumRootInports	    0
    NumRootOutports	    0
    ParameterArgumentNames  ""
    ComputedModelVersion    "1.106"
    NumModelReferences	    0
    NumTestPointedSignals   0
  }
  SavedCharacterEncoding  "ibm-5348_P100-1997"
  SaveDefaultBlockParams  on
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ShowTestPointIcons	  on
  ShowViewerIcons	  on
  SortedOrder		  off
  ExecutionContextIcon	  off
  ShowLinearizationAnnotations on
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  CovReportOnPause	  on
  ScopeRefreshTime	  0.035000
  OverrideScopeRefreshTime on
  DisableAllScopes	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Tue Jun 21 08:08:39 2005"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "umb"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Mon Oct 31 10:37:11 2005"
  ModelVersionFormat	  "1.%<AutoIncrement:106>"
  ConfigurationManager	  "None"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  ExtModeBatchMode	  off
  ExtModeEnableFloating	  on
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigDurationFloating "auto"
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  StrictBusMsg		  "None"
  ProdHWDeviceType	  "32-bit Generic"
  ShowModelReferenceBlockVersion off
  ShowModelReferenceBlockIO off
  Array {
    Type		    "Handle"
    Dimension		    1
    Simulink.ConfigSet {
      $ObjectID		      1
      Version		      "1.0.4"
      Array {
	Type			"Handle"
	Dimension		7
	Simulink.SolverCC {
	  $ObjectID		  2
	  Version		  "1.0.4"
	  StartTime		  "0.0"
	  StopTime		  "12"
	  AbsTol		  "auto"
	  FixedStep		  "auto"
	  InitialStep		  "auto"
	  MaxNumMinSteps	  "-1"
	  MaxOrder		  5
	  ExtrapolationOrder	  4
	  NumberNewtonIterations  1
	  MaxStep		  "auto"
	  MinStep		  "auto"
	  RelTol		  "1e-3"
	  SolverMode		  "SingleTasking"
	  Solver		  "FixedStepDiscrete"
	  SolverName		  "FixedStepDiscrete"
	  ZeroCrossControl	  "UseLocalSettings"
	  PositivePriorityOrder	  off
	  AutoInsertRateTranBlk	  off
	  SampleTimeConstraint	  "Unconstrained"
	  RateTranMode		  "Deterministic"
	}
	Simulink.DataIOCC {
	  $ObjectID		  3
	  Version		  "1.0.4"
	  Decimation		  "1"
	  ExternalInput		  "[t, u]"
	  FinalStateName	  "xFinal"
	  InitialState		  "xInitial"
	  LimitDataPoints	  on
	  MaxDataPoints		  "1000"
	  LoadExternalInput	  off
	  LoadInitialState	  off
	  SaveFinalState	  off
	  SaveFormat		  "Array"
	  SaveOutput		  on
	  SaveState		  off
	  SignalLogging		  on
	  SaveTime		  on
	  StateSaveName		  "xout"
	  TimeSaveName		  "tout"
	  OutputSaveName	  "yout"
	  SignalLoggingName	  "logsout"
	  OutputOption		  "RefineOutputTimes"
	  OutputTimes		  "[]"
	  Refine		  "1"
	}
	Simulink.OptimizationCC {
	  $ObjectID		  4
	  Array {
	    Type		    "Cell"
	    Dimension		    5
	    Cell		    "ZeroExternalMemoryAtStartup"
	    Cell		    "ZeroInternalMemoryAtStartup"
	    Cell		    "InitFltsAndDblsToZero"
	    Cell		    "OptimizeModelRefInitCode"
	    Cell		    "NoFixptDivByZeroProtection"
	    PropName		    "DisabledProps"
	  }
	  Version		  "1.0.4"
	  BlockReduction	  on
	  BooleanDataType	  on
	  ConditionallyExecuteInputs on
	  ConditionalExecOptimization "on_for_testing"
	  InlineParams		  off
	  InlineInvariantSignals  on
	  OptimizeBlockIOStorage  on
	  BufferReuse		  on
	  EnforceIntegerDowncast  on
	  ExpressionFolding	  on
	  FoldNonRolledExpr	  on
	  LocalBlockOutputs	  on
	  ParameterPooling	  on
	  RollThreshold		  5
	  SystemCodeInlineAuto	  off
	  StateBitsets		  off
	  DataBitsets		  off
	  UseTempVars		  off
	  ZeroExternalMemoryAtStartup on
	  ZeroInternalMemoryAtStartup on
	  InitFltsAndDblsToZero	  on
	  NoFixptDivByZeroProtection off
	  OptimizeModelRefInitCode off
	  LifeSpan		  "inf"
	}
	Simulink.DebuggingCC {
	  $ObjectID		  5
	  Version		  "1.0.4"
	  RTPrefix		  "error"
	  ConsistencyChecking	  "none"
	  ArrayBoundsChecking	  "none"
	  AlgebraicLoopMsg	  "warning"
	  ArtificialAlgebraicLoopMsg "warning"
	  CheckSSInitialOutputMsg on
	  CheckExecutionContextPreStartOutputMsg off
	  CheckExecutionContextRuntimeOutputMsg	off
	  SignalResolutionControl "TryResolveAllWithWarning"
	  BlockPriorityViolationMsg "warning"
	  MinStepSizeMsg	  "warning"
	  SolverPrmCheckMsg	  "none"
	  InheritedTsInSrcMsg	  "warning"
	  DiscreteInheritContinuousMsg "warning"
	  MultiTaskDSMMsg	  "warning"
	  MultiTaskRateTransMsg	  "error"
	  SingleTaskRateTransMsg  "none"
	  TasksWithSamePriorityMsg "warning"
	  CheckMatrixSingularityMsg "none"
	  IntegerOverflowMsg	  "warning"
	  Int32ToFloatConvMsg	  "warning"
	  ParameterDowncastMsg	  "error"
	  ParameterOverflowMsg	  "error"
	  ParameterPrecisionLossMsg "warning"
	  UnderSpecifiedDataTypeMsg "none"
	  UnnecessaryDatatypeConvMsg "none"
	  VectorMatrixConversionMsg "none"
	  InvalidFcnCallConnMsg	  "error"
	  FcnCallInpInsideContextMsg "Use local settings"
	  SignalLabelMismatchMsg  "none"
	  UnconnectedInputMsg	  "warning"
	  UnconnectedOutputMsg	  "warning"
	  UnconnectedLineMsg	  "warning"
	  SFcnCompatibilityMsg	  "none"
	  UniqueDataStoreMsg	  "none"
	  RootOutportRequireBusObject "warning"
	  AssertControl		  "UseLocalSettings"
	  EnableOverflowDetection off
	  ModelReferenceIOMsg	  "none"
	  ModelReferenceVersionMismatchMessage "none"
	  ModelReferenceIOMismatchMessage "none"
	  ModelReferenceCSMismatchMessage "none"
	  ModelReferenceSimTargetVerbose off
	  UnknownTsInhSupMsg	  "warning"
	  ModelReferenceDataLoggingMessage "warning"
	  ModelReferenceSymbolNameMessage "warning"
	}
	Simulink.HardwareCC {
	  $ObjectID		  6
	  Version		  "1.0.4"
	  ProdBitPerChar	  8
	  ProdBitPerShort	  16
	  ProdBitPerInt		  32
	  ProdBitPerLong	  32
	  ProdIntDivRoundTo	  "Undefined"
	  ProdEndianess		  "Unspecified"
	  ProdWordSize		  32
	  ProdShiftRightIntArith  on
	  ProdHWDeviceType	  "32-bit Generic"
	  TargetBitPerChar	  8
	  TargetBitPerShort	  16
	  TargetBitPerInt	  32
	  TargetBitPerLong	  32
	  TargetShiftRightIntArith on
	  TargetIntDivRoundTo	  "Undefined"
	  TargetEndianess	  "Unspecified"
	  TargetWordSize	  32
	  TargetTypeEmulationWarnSuppressLevel 0
	  TargetPreprocMaxBitsSint 32
	  TargetPreprocMaxBitsUint 32
	  TargetHWDeviceType	  "Specified"
	  TargetUnknown		  off
	  ProdEqTarget		  on
	}
	Simulink.ModelReferenceCC {
	  $ObjectID		  7
	  Version		  "1.0.4"
	  UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
	  CheckModelReferenceTargetMessage "error"
	  ModelReferenceNumInstancesAllowed "Multi"
	  ModelReferencePassRootInputsByReference on
	  ModelReferenceMinAlgLoopOccurrences off
	}
	Simulink.RTWCC {
	  $BackupClass		  "Simulink.RTWCC"
	  $ObjectID		  8
	  Array {
	    Type		    "Cell"
	    Dimension		    1
	    Cell		    "IncludeHyperlinkInReport"
	    PropName		    "DisabledProps"
	  }
	  Version		  "1.0.4"
	  SystemTargetFile	  "grt.tlc"
	  GenCodeOnly		  off
	  MakeCommand		  "make_rtw"
	  TemplateMakefile	  "grt_default_tmf"
	  GenerateReport	  off
	  SaveLog		  off
	  RTWVerbose		  on
	  RetainRTWFile		  off
	  ProfileTLC		  off
	  TLCDebug		  off
	  TLCCoverage		  off
	  TLCAssert		  off
	  ProcessScriptMode	  "Default"
	  ConfigurationMode	  "Optimized"
	  ConfigAtBuild		  off
	  IncludeHyperlinkInReport off
	  LaunchReport		  off
	  Array {
	    Type		    "Handle"
	    Dimension		    2
	    Simulink.CodeAppCC {
	      $ObjectID		      9
	      Array {
		Type			"Cell"
		Dimension		9
		Cell			"IgnoreCustomStorageClasses"
		Cell			"InsertBlockDesc"
		Cell			"SFDataObjDesc"
		Cell			"SimulinkDataObjDesc"
		Cell			"DefineNamingRule"
		Cell			"SignalNamingRule"
		Cell			"ParamNamingRule"
		Cell			"InlinedPrmAccess"
		Cell			"CustomSymbolStr"
		PropName		"DisabledProps"
	      }
	      Version		      "1.0.4"
	      ForceParamTrailComments off
	      GenerateComments	      on
	      IgnoreCustomStorageClasses on
	      IncHierarchyInIds	      off
	      MaxIdLength	      31
	      PreserveName	      off
	      PreserveNameWithParent  off
	      ShowEliminatedStatement off
	      IncAutoGenComments      off
	      SimulinkDataObjDesc     off
	      SFDataObjDesc	      off
	      IncDataTypeInIds	      off
	      PrefixModelToSubsysFcnNames on
	      CustomSymbolStr	      "$R$N$M"
	      MangleLength	      1
	      DefineNamingRule	      "None"
	      ParamNamingRule	      "None"
	      SignalNamingRule	      "None"
	      InsertBlockDesc	      off
	      SimulinkBlockComments   on
	      EnableCustomComments    off
	      InlinedPrmAccess	      "Literals"
	      ReqsInCode	      off
	    }
	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
	      $ObjectID		      10
	      Array {
		Type			"Cell"
		Dimension		12
		Cell			"IncludeMdlTerminateFcn"
		Cell			"CombineOutputUpdateFcns"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
	      }
	      Version		      "1.0.4"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    14
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Clock
      DisplayTime	      off
    }
    Block {
      BlockType		      DiscretePulseGenerator
      PulseType		      "Sample based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Period		      "2"
      PulseWidth	      "1"
      PhaseDelay	      "0"
      SampleTime	      "1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      Fcn
      Expr		      "sin(u[1])"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      SignalConversion
      OverrideOpt	      off
    }
    Block {
      BlockType		      Inport
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Lookup
      InputValues	      "[-4:5]"
      OutputValues	      " rand(1,10)-0.5"
      LookUpMeth	      "Interpolation-Extrapolation"
      OutDataTypeMode	      "Same as input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
      LUTDesignTableMode      "Redesign Table"
      LUTDesignDataSource     "Block Dialog"
      LUTDesignFunctionName   "sqrt(x)"
      LUTDesignUseExistingBP  on
      LUTDesignRelError	      "0.01"
      LUTDesignAbsError	      "1e-6"
    }
    Block {
      BlockType		      Mux
      Inputs		      "4"
      DisplayOption	      "none"
      BusObject		      "BusObject"
      NonVirtualBus	      off
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      Scope
      Floating		      off
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
    }
    Block {
      BlockType		      Step
      Time		      "1"
      Before		      "0"
      After		      "1"
      SampleTime	      "-1"
      VectorParams1D	      on
      ZeroCross		      on
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      UnitDelay
      X0		      "0"
      SampleTime	      "1"
      StateMustResolveToSignalObject off
      RTWStateStorageClass    "Auto"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    14
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    14
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "goertzel8"
    Location		    [31, 108, 862, 673]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "Altera Cyclone II EP2C35 DSP \nDevelopment Boar"
"d configuration"
      Ports		      []
      Position		      [13, 366, 179, 510]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "dspboard2C35_alteradspbuilder/Altera Cyclone II"
" EP2C35 DSP Development Board\nconfiguration"
      SourceType	      "DspBoard AlteraBlockSet"
      DspBoard		      "dspboard2C35"
      family		      "CYCLONEII"
      ClockPinIn	      "Pin_N2"
      Clock2PinOut	      "None"
      ClockPinOut	      "None"
      Clock3PinOut	      "None"
      Clock4PinOut	      "None"
      Clock5PinOut	      "None"
      GlobalResetPin	      "Any"
      Device		      "EP2C35F672C6"
      JTAGDevice	      "@1: EP2C23F1020 (0x003D064C)"
    }
    Block {
      BlockType		      DiscretePulseGenerator
      Name		      "Enable"
      Ports		      [0, 1]
      Position		      [20, 143, 65, 177]
      PulseType		      "Time based"
      Period		      "100"
      PulseWidth	      "8"
      PhaseDelay	      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Input Enable"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [150, 152, 215, 168]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Single Bit"
      nodetype		      "Input Port"
      bwl		      "1"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "InputEnable"
      ppat		      "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO"
"\\CCLI\\Lab7+8\\DSPBuilder_goertzel8"
      nSgCpl		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Input Start"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [145, 97, 210, 113]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Single Bit"
      nodetype		      "Input Port"
      bwl		      "1"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "InputStart"
      ppat		      "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO"
"\\CCLI\\Lab7+8\\DSPBuilder_goertzel8"
      nSgCpl		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Input x_im"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [150, 302, 215, 318]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Input Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Inputx_im"
      ppat		      "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO"
"\\CCLI\\Lab7+8\\DSPBuilder_goertzel8"
      nSgCpl		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Input x_re"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [150, 242, 215, 258]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Input Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Inputx_re"
      ppat		      "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO"
"\\CCLI\\Lab7+8\\DSPBuilder_goertzel8"
      nSgCpl		      "1"
    }
    Block {
      BlockType		      Mux
      Name		      "Mux"
      Ports		      [2, 1]
      Position		      [610, 43, 615, 127]
      ShowName		      off
      Inputs		      "2"
      DisplayOption	      "bar"
    }
    Block {
      BlockType		      Mux
      Name		      "Mux1"
      Ports		      [2, 1]
      Position		      [610, 163, 615, 247]
      ShowName		      off
      Inputs		      "2"
      DisplayOption	      "bar"
    }
    Block {
      BlockType		      Mux
      Name		      "Mux2"
      Ports		      [2, 1]
      Position		      [605, 278, 610, 362]
      ShowName		      off
      Inputs		      "2"
      DisplayOption	      "bar"
    }
    Block {
      BlockType		      Mux
      Name		      "Mux3"
      Ports		      [2, 1]
      Position		      [600, 398, 605, 482]
      ShowName		      off
      Inputs		      "2"
      DisplayOption	      "bar"
    }
    Block {
      BlockType		      Reference
      Name		      "Output y0_imag"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [490, 97, 555, 113]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output y0_real"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [495, 57, 560, 73]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output y1_imag"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [495, 217, 560, 233]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output y1_real"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [495, 177, 560, 193]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output y2_imag"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [490, 332, 555, 348]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output y2_real"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [490, 292, 555, 308]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output y3_imag"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [485, 452, 550, 468]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output y3_real"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [485, 412, 550, 428]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [8]
      Position		      [760, 19, 795, 476]
      Location		      [629, 55, 939, 738]
      Open		      on
      NumInputPorts	      "8"
      List {
	ListType		AxesTitles
	axes1			"Start"
	axes2			"Enable"
	axes3			"x_re"
	axes4			"x_im"
	axes5			"X[0]"
	axes6			"X[1]"
	axes7			"X[2]"
	axes8			"X[3]"
      }
      YMin		      "-0.2~-0.2~-2~-2~-10~-50~-50~-50"
      YMax		      "1.2~1.2~20~20~80~50~50~50"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [39, 13, 108, 60]
      ForegroundColor	      "blue"
      FontSize		      10
      SourceBlock	      "ALTELINK/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "DSP Board"
      opt		      "Speed"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO"
"\\CCLI\\Lab7+8"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
      UniqueVHDLHierarchyName off
      RegenerateIPFunctionalModel off
      RunUpdatedSimulation    on
      JTAGCable		      "USB-Blaster [USB-0]"
    }
    Block {
      BlockType		      Step
      Name		      "Start"
      Position		      [25, 90, 55, 120]
      Before		      "1"
      After		      "0"
      SampleTime	      "0"
    }
    Block {
      BlockType		      UnitDelay
      Name		      "Unit Delay"
      Position		      [80, 88, 115, 122]
      X0		      "1"
    }
    Block {
      BlockType		      UnitDelay
      Name		      "Unit Delay1"
      Position		      [85, 143, 120, 177]
    }
    Block {
      BlockType		      UnitDelay
      Name		      "Unit Delay2"
      Position		      [80, 233, 115, 267]
    }
    Block {
      BlockType		      UnitDelay
      Name		      "Unit Delay3"
      Position		      [85, 293, 120, 327]
    }
    Block {
      BlockType		      SubSystem
      Name		      "W0 Loop"
      Ports		      [4, 2]
      Position		      [345, 46, 440, 124]
      ForegroundColor	      "blue"
      AncestorBlock	      "ALTELINK/AltLab/HDL SubSystem"
      FontSize		      10
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskType		      "SubSystem AlteraBlockSet"
      MaskSelfModifiable      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"W0 Loop"
	Location		[199, 143, 928, 686]
	Open			on
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Xre[7:0]"
	  Position		  [30, 73, 60, 87]
	  ForegroundColor	  "blue"
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Xim[7:0]"
	  Position		  [25, 248, 55, 262]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Start"
	  Position		  [20, 343, 50, 357]
	  ForegroundColor	  "blue"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Enable"
	  Position		  [20, 403, 50, 417]
	  ForegroundColor	  "blue"
	  Port			  "4"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [85, 72, 150, 88]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 247, 145, 263]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input1"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input2"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [75, 342, 140, 358]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input2"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input3"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 402, 145, 418]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input3"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [560, 102, 625, 118]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [560, 277, 625, 293]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Yre[7:0]"
	  Position		  [655, 103, 685, 117]
	  ForegroundColor	  "blue"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Yim[7:0]"
	  Position		  [655, 278, 685, 292]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "Xim[7:0]"
	  SrcPort		  1
	  DstBlock		  "Input1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Output"
	  SrcPort		  1
	  DstBlock		  "Yre[7:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Xre[7:0]"
	  SrcPort		  1
	  DstBlock		  "Input"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Output1"
	  SrcPort		  1
	  DstBlock		  "Yim[7:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Start"
	  SrcPort		  1
	  DstBlock		  "Input2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Enable"
	  SrcPort		  1
	  DstBlock		  "Input3"
	  DstPort		  1
	}
	Annotation {
	  Name			  "Complex IIR Goertzel loop for w^0=1."
	  Position		  [254, 31]
	  DropShadow		  on
	  TeXMode		  "on"
	  FontName		  "Arial"
	  FontSize		  12
	  FontWeight		  "bold"
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "W1 Loop"
      Ports		      [4, 2]
      Position		      [345, 164, 440, 246]
      ForegroundColor	      "blue"
      AncestorBlock	      "ALTELINK/AltLab/HDL SubSystem"
      FontSize		      10
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskType		      "SubSystem AlteraBlockSet"
      MaskSelfModifiable      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"W1 Loop"
	Location		[46, 109, 1011, 720]
	Open			on
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Xre[7:0]"
	  Position		  [30, 73, 60, 87]
	  ForegroundColor	  "blue"
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Xim[7:0]"
	  Position		  [25, 253, 55, 267]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Start"
	  Position		  [20, 348, 50, 362]
	  ForegroundColor	  "blue"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Enable"
	  Position		  [20, 403, 50, 417]
	  ForegroundColor	  "blue"
	  Port			  "4"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [85, 72, 150, 88]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 252, 145, 268]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input1"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input2"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [75, 347, 140, 363]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input2"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input3"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 402, 145, 418]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input3"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [795, 102, 860, 118]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [780, 457, 845, 473]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Yre[7:0]"
	  Position		  [890, 103, 920, 117]
	  ForegroundColor	  "blue"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Yim[7:0]"
	  Position		  [875, 458, 905, 472]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "Xim[7:0]"
	  SrcPort		  1
	  DstBlock		  "Input1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Output"
	  SrcPort		  1
	  DstBlock		  "Yre[7:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Xre[7:0]"
	  SrcPort		  1
	  DstBlock		  "Input"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Output1"
	  SrcPort		  1
	  DstBlock		  "Yim[7:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Start"
	  SrcPort		  1
	  DstBlock		  "Input2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Enable"
	  SrcPort		  1
	  DstBlock		  "Input3"
	  DstPort		  1
	}
	Annotation {
	  Name			  "Complex IIR Goertzel loop for w^1=exp(-j*\\"
"pi/4)."
	  Position		  [284, 31]
	  DropShadow		  on
	  TeXMode		  "on"
	  FontName		  "Arial"
	  FontSize		  12
	  FontWeight		  "bold"
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "W2 Loop"
      Ports		      [4, 2]
      Position		      [345, 281, 440, 359]
      ForegroundColor	      "blue"
      AncestorBlock	      "ALTELINK/AltLab/HDL SubSystem"
      FontSize		      10
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskType		      "SubSystem AlteraBlockSet"
      MaskSelfModifiable      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"W2 Loop"
	Location		[48, 141, 971, 667]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Xre[7:0]"
	  Position		  [30, 73, 60, 87]
	  ForegroundColor	  "blue"
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Xim[7:0]"
	  Position		  [25, 248, 55, 262]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Start"
	  Position		  [20, 353, 50, 367]
	  ForegroundColor	  "blue"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Enable"
	  Position		  [20, 403, 50, 417]
	  ForegroundColor	  "blue"
	  Port			  "4"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [85, 72, 150, 88]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 247, 145, 263]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input1"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input2"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [75, 352, 140, 368]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input2"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input3"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 402, 145, 418]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input3"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [565, 272, 630, 288]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [585, 102, 650, 118]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Yre[7:0]"
	  Position		  [660, 273, 690, 287]
	  ForegroundColor	  "blue"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Yim[7:0]"
	  Position		  [680, 103, 710, 117]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "Xim[7:0]"
	  SrcPort		  1
	  DstBlock		  "Input1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Output"
	  SrcPort		  1
	  DstBlock		  "Yre[7:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Xre[7:0]"
	  SrcPort		  1
	  DstBlock		  "Input"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Output1"
	  SrcPort		  1
	  DstBlock		  "Yim[7:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Start"
	  SrcPort		  1
	  DstBlock		  "Input2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Enable"
	  SrcPort		  1
	  DstBlock		  "Input3"
	  DstPort		  1
	}
	Annotation {
	  Name			  "Complex IIR Goertzel loop for w^2=-j."
	  Position		  [254, 31]
	  DropShadow		  on
	  TeXMode		  "on"
	  FontName		  "Arial"
	  FontSize		  12
	  FontWeight		  "bold"
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "W3 Loop"
      Ports		      [4, 2]
      Position		      [345, 399, 440, 481]
      ForegroundColor	      "blue"
      AncestorBlock	      "ALTELINK/AltLab/HDL SubSystem"
      FontSize		      10
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskType		      "SubSystem AlteraBlockSet"
      MaskSelfModifiable      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"W3 Loop"
	Location		[48, 141, 1009, 700]
	Open			on
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Xre[7:0]"
	  Position		  [30, 73, 60, 87]
	  ForegroundColor	  "blue"
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Xim[7:0]"
	  Position		  [25, 253, 55, 267]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Start"
	  Position		  [20, 353, 50, 367]
	  ForegroundColor	  "blue"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Enable"
	  Position		  [20, 403, 50, 417]
	  ForegroundColor	  "blue"
	  Port			  "4"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [85, 72, 150, 88]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 252, 145, 268]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input1"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input2"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [75, 352, 140, 368]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input2"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Input3"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 402, 145, 418]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "1"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Input3"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [795, 102, 860, 118]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Output1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [780, 457, 845, 473]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Yre[7:0]"
	  Position		  [890, 103, 920, 117]
	  ForegroundColor	  "blue"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Yim[7:0]"
	  Position		  [875, 458, 905, 472]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "Xim[7:0]"
	  SrcPort		  1
	  DstBlock		  "Input1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Output"
	  SrcPort		  1
	  DstBlock		  "Yre[7:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Xre[7:0]"
	  SrcPort		  1
	  DstBlock		  "Input"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Output1"
	  SrcPort		  1
	  DstBlock		  "Yim[7:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Start"
	  SrcPort		  1
	  DstBlock		  "Input2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Enable"
	  SrcPort		  1
	  DstBlock		  "Input3"
	  DstPort		  1
	}
	Annotation {
	  Name			  "Complex IIR Goertzel loop for w^3=exp(-j3\\"
"pi/4)."
	  Position		  [284, 31]
	  DropShadow		  on
	  TeXMode		  "on"
	  FontName		  "Arial"
	  FontSize		  12
	  FontWeight		  "bold"
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "x_im"
      Ports		      [0, 1]
      Position		      [25, 295, 55, 325]
      SourceBlock	      "simulink/Sources/Repeating\nSequence"
      SourceType	      "Repeating table"
      ShowPortLabels	      on
      rep_seq_t		      "[0 1 2 3 4 5 6 7 8 9  10   100]"
      rep_seq_y		      "[ 0 16 14 12 10 8 6 4 2 2  2 2]"
    }
    Block {
      BlockType		      Reference
      Name		      "x_re "
      Ports		      [0, 1]
      Position		      [25, 235, 55, 265]
      SourceBlock	      "simulink/Sources/Repeating\nSequence"
      SourceType	      "Repeating table"
      ShowPortLabels	      on
      rep_seq_t		      "[0 1 2 3 4 5 6 7 8 9 10  100]"
      rep_seq_y		      "[ 0 16 14 12 10 8 6 4 2 0 0 0]"
    }
    Line {
      SrcBlock		      "x_re "
      SrcPort		      1
      DstBlock		      "Unit Delay2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Start"
      SrcPort		      1
      DstBlock		      "Unit Delay"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Enable"
      SrcPort		      1
      DstBlock		      "Unit Delay1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Input x_re"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	Points			[0, -75]
	Branch {
	  DstBlock		  "W1 Loop"
	  DstPort		  1
	}
	Branch {
	  Points		  [0, -120]
	  Branch {
	    Points		    [0, -45; 465, 0; 0, 155]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "W0 Loop"
	    DstPort		    1
	  }
	}
      }
      Branch {
	Points			[0, 40]
	Branch {
	  DstBlock		  "W2 Loop"
	  DstPort		  1
	}
	Branch {
	  Points		  [0, 120]
	  DstBlock		  "W3 Loop"
	  DstPort		  1
	}
      }
    }
    Line {
      SrcBlock		      "x_im"
      SrcPort		      1
      DstBlock		      "Unit Delay3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Input x_im"
      SrcPort		      1
      Points		      [20, 0]
      Branch {
	Points			[0, -115]
	Branch {
	  DstBlock		  "W1 Loop"
	  DstPort		  2
	}
	Branch {
	  Points		  [0, -120]
	  Branch {
	    Points		    [0, -60; 450, 0; 0, 205]
	    DstBlock		    "Scope"
	    DstPort		    4
	  }
	  Branch {
	    DstBlock		    "W0 Loop"
	    DstPort		    2
	  }
	}
      }
      Branch {
	Points			[0, 120]
	DstBlock		"W3 Loop"
	DstPort			2
      }
      Branch {
	DstBlock		"W2 Loop"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Input Start"
      SrcPort		      1
      Points		      [35, 0; 0, 0]
      Branch {
	Points			[0, -85; 430, 0; 0, 35]
	DstBlock		"Scope"
	DstPort			1
      }
      Branch {
	Points			[0, -10]
	Branch {
	  DstBlock		  "W0 Loop"
	  DstPort		  3
	}
	Branch {
	  Points		  [0, 120]
	  Branch {
	    DstBlock		    "W1 Loop"
	    DstPort		    3
	  }
	  Branch {
	    Points		    [0, 115]
	    Branch {
	      DstBlock		      "W2 Loop"
	      DstPort		      3
	    }
	    Branch {
	      Points		      [0, 120]
	      DstBlock		      "W3 Loop"
	      DstPort		      3
	    }
	  }
	}
      }
    }
    Line {
      SrcBlock		      "Input Enable"
      SrcPort		      1
      Points		      [45, 0]
      Branch {
	Points			[0, -45]
	Branch {
	  DstBlock		  "W0 Loop"
	  DstPort		  4
	}
	Branch {
	  Points		  [0, -90; 440, 0; 0, 85]
	  DstBlock		  "Scope"
	  DstPort		  2
	}
      }
      Branch {
	Points			[0, 75]
	Branch {
	  DstBlock		  "W1 Loop"
	  DstPort		  4
	}
	Branch {
	  Points		  [0, 115]
	  Branch {
	    DstBlock		    "W2 Loop"
	    DstPort		    4
	  }
	  Branch {
	    Points		    [0, 120]
	    DstBlock		    "W3 Loop"
	    DstPort		    4
	  }
	}
      }
    }
    Line {
      SrcBlock		      "W0 Loop"
      SrcPort		      1
      DstBlock		      "Output y0_real"
      DstPort		      1
    }
    Line {
      SrcBlock		      "W0 Loop"
      SrcPort		      2
      DstBlock		      "Output y0_imag"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Unit Delay"
      SrcPort		      1
      DstBlock		      "Input Start"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Unit Delay1"
      SrcPort		      1
      DstBlock		      "Input Enable"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Unit Delay2"
      SrcPort		      1
      DstBlock		      "Input x_re"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Unit Delay3"
      SrcPort		      1
      DstBlock		      "Input x_im"
      DstPort		      1
    }
    Line {
      SrcBlock		      "W1 Loop"
      SrcPort		      1
      DstBlock		      "Output y1_real"
      DstPort		      1
    }
    Line {
      SrcBlock		      "W1 Loop"
      SrcPort		      2
      DstBlock		      "Output y1_imag"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output y0_real"
      SrcPort		      1
      DstBlock		      "Mux"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output y0_imag"
      SrcPort		      1
      DstBlock		      "Mux"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Mux"
      SrcPort		      1
      Points		      [55, 0; 0, 190]
      DstBlock		      "Scope"
      DstPort		      5
    }
    Line {
      SrcBlock		      "Output y1_real"
      SrcPort		      1
      DstBlock		      "Mux1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output y1_imag"
      SrcPort		      1
      DstBlock		      "Mux1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Mux1"
      SrcPort		      1
      Points		      [40, 0; 0, 125]
      DstBlock		      "Scope"
      DstPort		      6
    }
    Line {
      SrcBlock		      "Output y2_real"
      SrcPort		      1
      DstBlock		      "Mux2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output y2_imag"
      SrcPort		      1
      DstBlock		      "Mux2"
      DstPort		      2
    }
    Line {
      SrcBlock		      "W2 Loop"
      SrcPort		      1
      DstBlock		      "Output y2_real"
      DstPort		      1
    }
    Line {
      SrcBlock		      "W2 Loop"
      SrcPort		      2
      DstBlock		      "Output y2_imag"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output y3_real"
      SrcPort		      1
      DstBlock		      "Mux3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output y3_imag"
      SrcPort		      1
      DstBlock		      "Mux3"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Mux2"
      SrcPort		      1
      Points		      [30, 0; 0, 65]
      DstBlock		      "Scope"
      DstPort		      7
    }
    Line {
      SrcBlock		      "Mux3"
      SrcPort		      1
      DstBlock		      "Scope"
      DstPort		      8
    }
    Line {
      SrcBlock		      "W3 Loop"
      SrcPort		      1
      DstBlock		      "Output y3_real"
      DstPort		      1
    }
    Line {
      SrcBlock		      "W3 Loop"
      SrcPort		      2
      DstBlock		      "Output y3_imag"
      DstPort		      1
    }
  }
}