Model { Name "dif8" Version 6.1 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.54" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "ibm-5348_P100-1997" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Wed Oct 26 10:33:24 2005" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "umb" ModifiedDateFormat "%" LastModifiedDate "Wed Oct 26 17:12:48 2005" ModelVersionFormat "1.%" ConfigurationManager "None" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on StrictBusMsg "None" ProdHWDeviceType "32-bit Generic" ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.0.4" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.0.4" StartTime "0.0" StopTime "20.0" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" RelTol "1e-3" SolverMode "SingleTasking" Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" ZeroCrossControl "UseLocalSettings" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" RateTranMode "Deterministic" } Simulink.DataIOCC { $ObjectID 3 Version "1.0.4" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.0.4" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on ConditionalExecOptimization "on_for_testing" InlineParams off InlineInvariantSignals on OptimizeBlockIOStorage on BufferReuse on EnforceIntegerDowncast on ExpressionFolding on FoldNonRolledExpr on LocalBlockOutputs on ParameterPooling on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off OptimizeModelRefInitCode off LifeSpan "inf" } Simulink.DebuggingCC { $ObjectID 5 Version "1.0.4" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.0.4" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.0.4" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.0.4" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 9 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" PropName "DisabledProps" } Version "1.0.4" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off PrefixModelToSubsysFcnNames on CustomSymbolStr "$R$N$M" MangleLength 1 DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 12 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" PropName "DisabledProps" } Version "1.0.4" TargetFcnLib "ansi_tfl_tmw.mat" GenFloatMathFcnCalls "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off IsPILTarget off ModelReferenceCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" SimulationMode "normal" CurrentDlgPage "Solver" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 14 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Clock DisplayTime off } Block { BlockType Constant Value "1" VectorParams1D on OutDataTypeMode "Inherit from 'Constant value'" OutDataType "sfix(16)" ConRadixGroup "Use specified scaling" OutScaling "2^0" SampleTime "inf" } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Fcn Expr "sin(u[1])" SampleTime "-1" } Block { BlockType SignalConversion OverrideOpt off } Block { BlockType Inport BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Lookup InputValues "[-4:5]" OutputValues " rand(1,10)-0.5" LookUpMeth "Interpolation-Extrapolation" OutDataTypeMode "Same as input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" LUTDesignTableMode "Redesign Table" LUTDesignDataSource "Block Dialog" LUTDesignFunctionName "sqrt(x)" LUTDesignUseExistingBP on LUTDesignRelError "0.01" LUTDesignAbsError "1e-6" } Block { BlockType Outport Port "1" BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Reference } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType "S-Function" FunctionName "system" SFunctionModules "''" PortCounts "[]" } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" PermitHierarchicalResolution "All" SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "dif8" Location [23, 78, 1007, 679] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "86" ReportName "simulink-default.rpt" Block { BlockType Reference Name "Altera Cyclone II EP2C35 DSP \nDevelopment Boar" "d configuration" Ports [] Position [13, 441, 179, 585] ForegroundColor "blue" FontSize 10 SourceBlock "dspboard2C35_alteradspbuilder/Altera Cyclone II" " EP2C35 DSP Development Board\nconfiguration" SourceType "DspBoard AlteraBlockSet" DspBoard "dspboard2C35" family "CYCLONEII" ClockPinIn "Pin_N2" Clock2PinOut "None" ClockPinOut "None" Clock3PinOut "None" Clock4PinOut "None" Clock5PinOut "None" GlobalResetPin "Any" Device "EP2C35F672C6" JTAGDevice "@1: EP2C23F1020 (0x003D064C)" } Block { BlockType Reference Name "Enable" Description "Sign Binary Fractionnal" Ports [1, 1] Position [110, 217, 175, 233] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Single Bit" nodetype "Input Port" bwl "1" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Enable" ppat "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO" "\\CCLI\\lab7+8\\DSPBuilder_dif8" nSgCpl "1" } Block { BlockType Scope Name "Imag Scope" Ports [8] Position [1075, 323, 1115, 602] Location [28, 68, 357, 631] Open off NumInputPorts "8" List { ListType AxesTitles axes1 "X[0]" axes2 "X[1]" axes3 "X[3]" axes4 "X[4]" axes5 "X[5]" axes6 "X[6]" axes7 "X[6]" axes8 "X[7]" } YMin "-22~-22~-22~-22~-22~-22~-22~-22" YMax "22~22~22~22~22~22~22~22" SaveName "ScopeData1" DataFormat "StructureWithTime" } Block { BlockType Reference Name "Input Im" Description "Sign Binary Fractionnal" Ports [1, 1] Position [115, 392, 180, 408] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "InputIm" ppat "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO" "\\CCLI\\lab7+8\\DSPBuilder_dif8" nSgCpl "1" } Block { BlockType Reference Name "Input Re" Description "Sign Binary Fractionnal" Ports [1, 1] Position [115, 92, 180, 108] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "InputRe" ppat "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO" "\\CCLI\\lab7+8\\DSPBuilder_dif8" nSgCpl "1" } Block { BlockType Reference Name "Output Xim0" Description "Sign Binary Fractionnal" Ports [1, 1] Position [990, 332, 1055, 348] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xim1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [990, 367, 1055, 383] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xim2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [995, 402, 1050, 418] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xim3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [990, 437, 1055, 453] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xim4" Description "Sign Binary Fractionnal" Ports [1, 1] Position [985, 472, 1050, 488] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xim5" Description "Sign Binary Fractionnal" Ports [1, 1] Position [990, 507, 1055, 523] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xim6" Description "Sign Binary Fractionnal" Ports [1, 1] Position [990, 542, 1055, 558] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xim7" Description "Sign Binary Fractionnal" Ports [1, 1] Position [990, 577, 1055, 593] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xre0" Description "Sign Binary Fractionnal" Ports [1, 1] Position [985, 22, 1050, 38] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xre1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [985, 57, 1050, 73] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xre2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [985, 92, 1050, 108] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xre3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [985, 127, 1050, 143] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xre4" Description "Sign Binary Fractionnal" Ports [1, 1] Position [985, 162, 1050, 178] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xre5" Description "Sign Binary Fractionnal" Ports [1, 1] Position [985, 197, 1050, 213] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xre6" Description "Sign Binary Fractionnal" Ports [1, 1] Position [985, 232, 1050, 248] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output Xre7" Description "Sign Binary Fractionnal" Ports [1, 1] Position [990, 267, 1050, 283] ForegroundColor "blue" FontSize 10 SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator" Ports [0, 1] Position [40, 208, 85, 242] Period "100" PulseWidth "8" PhaseDelay "2" } Block { BlockType Scope Name "Real Scope" Ports [8] Position [1070, 13, 1110, 292] Location [36, 75, 365, 638] Open off NumInputPorts "8" List { ListType AxesTitles axes1 "X[0]" axes2 "X[1]" axes3 "X[3]" axes4 "X[4]" axes5 "X[5]" axes6 "X[6]" axes7 "X[6]" axes8 "X[7]" } YMin "0~-12~-12~-12~-12~-12~-12~-12" YMax "100~12~12~12~12~12~12~12" DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope W1" Ports [4] Position [515, 122, 550, 168] Location [133, 78, 483, 644] Open off NumInputPorts "4" List { ListType AxesTitles axes1 "Dre" axes2 "Dim" axes3 "Ere" axes4 "Eim" } YMin "-5~-5~-5~-5" YMax "5~5~5~5" SaveName "ScopeData4" DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope W3" Ports [4] Position [550, 562, 585, 608] Location [133, 78, 483, 644] Open off NumInputPorts "4" List { ListType AxesTitles axes1 "Dre" axes2 "Dim" axes3 "Ere" axes4 "Eim" } YMin "-5~-5~-5~-5" YMax "5~5~5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" } Block { BlockType Reference Name "Shift Taps Imag" Ports [2, 8] Position [210, 334, 270, 586] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Shift Taps" SourceType "ShiftTaps Altera Blockset" bwaddr "8" depth "1" cst off clken on eab "None" } Block { BlockType Reference Name "Shift Taps Real" Ports [2, 8] Position [210, 34, 270, 286] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Shift Taps" SourceType "ShiftTaps Altera Blockset" bwaddr "8" depth "1" cst off clken on eab "None" } Block { BlockType Reference Name "SignalCompiler" Ports [] Position [44, 13, 113, 60] ForegroundColor "blue" FontSize 10 SourceBlock "ALTELINK/AltLab/SignalCompiler" SourceType "SignalCompiler" family "Stratix" opt "Speed" synthtool "Others" vstim on SynthAct "None" workdir "C:\\Documents and Settings\\umb\\Uwe\\tex\\PRO" "\\CCLI\\lab7+8" Procetype "prod" UseReset on ResetPin "Active High" ClockPin "Output to Pin" ClockPeriod "20" UseSignalTap off CreatePtfFile off SignalTapDepth "128" VerilogSupport off UniqueVHDLHierarchyName off RegenerateIPFunctionalModel off RunUpdatedSimulation on JTAGCable "USB-Blaster [USB-0]" } Block { BlockType SubSystem Name "W0 Butterfly 1. stage" Ports [4, 4] Position [375, 46, 470, 124] ForegroundColor "blue" AncestorBlock "ALTELINK/AltLab/HDL SubSystem" FontSize 10 TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "SubSystem AlteraBlockSet" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" System { Name "W0 Butterfly 1. stage" Location [48, 141, 971, 622] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "Are[7:0]" Position [30, 73, 60, 87] ForegroundColor "blue" Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Aim[7:0]" Position [30, 168, 60, 182] ForegroundColor "blue" Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bre[7:0]" Position [30, 248, 60, 262] ForegroundColor "blue" Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bim[7:0]" Position [30, 333, 60, 347] ForegroundColor "blue" Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Aim minus Bim" Ports [2, 1] Position [445, 328, 485, 392] ForegroundColor "blue" FontSize 10 SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su" "btractor" SourceType "Sum AlteraBlockSet" Inputs "2" direction "+-" pipeline "off" clken "off" MaskValue "1" } Block { BlockType Reference Name "Aim plus Bim" Ports [2, 1] Position [445, 138, 485, 202] ForegroundColor "blue" FontSize 10 SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su" "btractor" SourceType "Sum AlteraBlockSet" Inputs "2" direction "+" pipeline "off" clken "off" MaskValue "1" } Block { BlockType Reference Name "Are minus Bre" Ports [2, 1] Position [445, 238, 485, 302] ForegroundColor "blue" FontSize 10 SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su" "btractor" SourceType "Sum AlteraBlockSet" Inputs "2" direction "+-" pipeline "off" clken "off" MaskValue "1" } Block { BlockType Reference Name "Are plus Bre" Ports [2, 1] Position [445, 43, 485, 107] ForegroundColor "blue" FontSize 10 SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su" "btractor" SourceType "Sum AlteraBlockSet" Inputs "2" direction "+" pipeline "off" clken "off" MaskValue "1" } Block { BlockType Reference Name "Input" Description "Sign Binary Fractionnal" Ports [1, 1] Position [85, 72, 150, 88] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Input" nSgCpl "0" } Block { BlockType Reference Name "Input1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 167, 145, 183] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Input1" nSgCpl "0" } Block { BlockType Reference Name "Input2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 247, 145, 263] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Input2" nSgCpl "0" } Block { BlockType Reference Name "Input3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 332, 145, 348] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Input3" nSgCpl "0" } Block { BlockType Reference Name "Output" Description "Sign Binary Fractionnal" Ports [1, 1] Position [730, 67, 795, 83] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [730, 162, 795, 178] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [735, 262, 800, 278] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [735, 352, 800, 368] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Outport Name "Dre[7:0]" Position [825, 68, 855, 82] ForegroundColor "blue" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Dim[7:0]" Position [825, 163, 855, 177] ForegroundColor "blue" Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Ere[7:0]" Position [830, 263, 860, 277] ForegroundColor "blue" Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Eim[7:0]" Position [830, 353, 860, 367] ForegroundColor "blue" Port "4" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "Aim[7:0]" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "Dre[7:0]" DstPort 1 } Line { SrcBlock "Are[7:0]" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output1" SrcPort 1 DstBlock "Dim[7:0]" DstPort 1 } Line { SrcBlock "Bre[7:0]" SrcPort 1 DstBlock "Input2" DstPort 1 } Line { SrcBlock "Bim[7:0]" SrcPort 1 DstBlock "Input3" DstPort 1 } Line { SrcBlock "Output2" SrcPort 1 DstBlock "Ere[7:0]" DstPort 1 } Line { SrcBlock "Output3" SrcPort 1 DstBlock "Eim[7:0]" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 Points [135, 0; 0, -20; 25, 0] Branch { DstBlock "Are plus Bre" DstPort 1 } Branch { Points [0, 195] DstBlock "Are minus Bre" DstPort 1 } } Line { SrcBlock "Input2" SrcPort 1 Points [0, 0; 140, 0] Branch { Points [0, -165] DstBlock "Are plus Bre" DstPort 2 } Branch { Points [0, 30] DstBlock "Are minus Bre" DstPort 2 } } Line { SrcBlock "Input1" SrcPort 1 Points [0, 0; 115, 0] Branch { Points [80, 0; 0, -20] DstBlock "Aim plus Bim" DstPort 1 } Branch { Points [0, 170] DstBlock "Aim minus Bim" DstPort 1 } } Line { SrcBlock "Input3" SrcPort 1 Points [0, 0; 105, 0] Branch { Points [90, 0; 0, -155] DstBlock "Aim plus Bim" DstPort 2 } Branch { Points [0, 35] DstBlock "Aim minus Bim" DstPort 2 } } Line { SrcBlock "Are plus Bre" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Aim plus Bim" SrcPort 1 DstBlock "Output1" DstPort 1 } Line { SrcBlock "Are minus Bre" SrcPort 1 DstBlock "Output2" DstPort 1 } Line { SrcBlock "Aim minus Bim" SrcPort 1 DstBlock "Output3" DstPort 1 } Annotation { Name "Complex butterfly for w^0=1." Position [444, 16] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } Block { BlockType SubSystem Name "W1 Butterfly 1.stage" Ports [4, 4] Position [375, 181, 470, 259] ForegroundColor "blue" AncestorBlock "ALTELINK/AltLab/HDL SubSystem" FontSize 10 TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "SubSystem AlteraBlockSet" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" System { Name "W1 Butterfly 1.stage" Location [48, 77, 986, 688] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "Are[7:0]" Position [30, 78, 60, 92] ForegroundColor "blue" Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Aim[7:0]" Position [30, 173, 60, 187] ForegroundColor "blue" Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bre[7:0]" Position [30, 253, 60, 267] ForegroundColor "blue" Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bim[7:0]" Position [30, 338, 60, 352] ForegroundColor "blue" Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Input" Description "Sign Binary Fractionnal" Ports [1, 1] Position [85, 77, 150, 93] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input" nSgCpl "0" } Block { BlockType Reference Name "Input1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 172, 145, 188] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input1" nSgCpl "0" } Block { BlockType Reference Name "Input2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 252, 145, 268] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input2" nSgCpl "0" } Block { BlockType Reference Name "Input3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 337, 145, 353] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input3" nSgCpl "0" } Block { BlockType Reference Name "Output" Description "Sign Binary Fractionnal" Ports [1, 1] Position [730, 72, 795, 88] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [730, 167, 795, 183] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [745, 347, 810, 363] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [750, 472, 815, 488] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "c minus s" Description "Sign Binary Fractionnal" Ports [0, 1] Position [95, 531, 145, 549] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Constant" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Constant" bwl "9" bwr "0" sat off rnd off bp off mask_cst "0" ncstsamp "1" cst "0" modulename "Constant" nSgCpl "0" } Block { BlockType Reference Name "c plus s" Description "Sign Binary Fractionnal" Ports [0, 1] Position [95, 476, 145, 494] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Constant" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Constant" bwl "9" bwr "0" sat off rnd off bp off mask_cst "0" ncstsamp "1" cst "0" modulename "Constant" nSgCpl "0" } Block { BlockType Reference Name "cos" Description "Sign Binary Fractionnal" Ports [0, 1] Position [95, 426, 145, 444] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Constant" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Constant" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" ncstsamp "1" cst "0" modulename "Constant" nSgCpl "0" } Block { BlockType Outport Name "Dre[7:0]" Position [825, 73, 855, 87] ForegroundColor "blue" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Dim[7:0]" Position [825, 168, 855, 182] ForegroundColor "blue" Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Ere[7:0]" Position [840, 348, 870, 362] ForegroundColor "blue" Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Eim[7:0]" Position [845, 473, 875, 487] ForegroundColor "blue" Port "4" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "Aim[7:0]" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "Dre[7:0]" DstPort 1 } Line { SrcBlock "Are[7:0]" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output1" SrcPort 1 DstBlock "Dim[7:0]" DstPort 1 } Line { SrcBlock "Bre[7:0]" SrcPort 1 DstBlock "Input2" DstPort 1 } Line { SrcBlock "Bim[7:0]" SrcPort 1 DstBlock "Input3" DstPort 1 } Line { SrcBlock "Output2" SrcPort 1 DstBlock "Ere[7:0]" DstPort 1 } Line { SrcBlock "Output3" SrcPort 1 DstBlock "Eim[7:0]" DstPort 1 } Annotation { Name "Complex butterfly for w^1=exp(-j*\\pi/4)." Position [444, 21] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } Block { BlockType SubSystem Name "W2 Butterfly 1. stage" Ports [4, 4] Position [390, 341, 485, 419] ForegroundColor "blue" AncestorBlock "ALTELINK/AltLab/HDL SubSystem" FontSize 10 TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "SubSystem AlteraBlockSet" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" System { Name "W2 Butterfly 1. stage" Location [48, 141, 971, 622] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "Are[7:0]" Position [30, 78, 60, 92] ForegroundColor "blue" Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Aim[7:0]" Position [30, 173, 60, 187] ForegroundColor "blue" Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bre[7:0]" Position [30, 253, 60, 267] ForegroundColor "blue" Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bim[7:0]" Position [30, 338, 60, 352] ForegroundColor "blue" Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Aim plus Bim" Ports [2, 1] Position [445, 143, 485, 207] ForegroundColor "blue" FontSize 10 SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su" "btractor" SourceType "Sum AlteraBlockSet" Inputs "2" direction "+" pipeline "off" clken "off" MaskValue "1" } Block { BlockType Reference Name "Are plus Bre" Ports [2, 1] Position [445, 48, 485, 112] ForegroundColor "blue" FontSize 10 SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su" "btractor" SourceType "Sum AlteraBlockSet" Inputs "2" direction "+" pipeline "off" clken "off" MaskValue "1" } Block { BlockType Reference Name "Bim minus Aim" Ports [2, 1] Position [445, 348, 485, 412] ForegroundColor "blue" FontSize 10 SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su" "btractor" SourceType "Sum AlteraBlockSet" Inputs "2" direction "-+" pipeline "off" clken "off" MaskValue "1" } Block { BlockType Reference Name "Bre minus Are" Ports [2, 1] Position [445, 243, 485, 307] ForegroundColor "blue" FontSize 10 SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su" "btractor" SourceType "Sum AlteraBlockSet" Inputs "2" direction "-+" pipeline "off" clken "off" MaskValue "1" } Block { BlockType Reference Name "Input" Description "Sign Binary Fractionnal" Ports [1, 1] Position [85, 77, 150, 93] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Input" nSgCpl "0" } Block { BlockType Reference Name "Input1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 172, 145, 188] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Input1" nSgCpl "0" } Block { BlockType Reference Name "Input2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 252, 145, 268] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Input2" nSgCpl "0" } Block { BlockType Reference Name "Input3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 337, 145, 353] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Input3" nSgCpl "0" } Block { BlockType Reference Name "Output" Description "Sign Binary Fractionnal" Ports [1, 1] Position [730, 72, 795, 88] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [730, 167, 795, 183] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [735, 267, 800, 283] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [735, 357, 800, 373] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat "off" rnd "off" bp "off" mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Outport Name "Dre[7:0]" Position [825, 73, 855, 87] ForegroundColor "blue" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Dim[7:0]" Position [825, 168, 855, 182] ForegroundColor "blue" Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Ere[7:0]" Position [830, 268, 860, 282] ForegroundColor "blue" Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Eim[7:0]" Position [830, 358, 860, 372] ForegroundColor "blue" Port "4" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "Aim[7:0]" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "Dre[7:0]" DstPort 1 } Line { SrcBlock "Are[7:0]" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output1" SrcPort 1 DstBlock "Dim[7:0]" DstPort 1 } Line { SrcBlock "Bre[7:0]" SrcPort 1 DstBlock "Input2" DstPort 1 } Line { SrcBlock "Bim[7:0]" SrcPort 1 DstBlock "Input3" DstPort 1 } Line { SrcBlock "Output2" SrcPort 1 DstBlock "Ere[7:0]" DstPort 1 } Line { SrcBlock "Output3" SrcPort 1 DstBlock "Eim[7:0]" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 Points [135, 0; 0, -20; 25, 0] Branch { DstBlock "Are plus Bre" DstPort 1 } Branch { Points [0, 195] DstBlock "Bre minus Are" DstPort 1 } } Line { SrcBlock "Input2" SrcPort 1 Points [0, 0; 140, 0] Branch { Points [0, -165] DstBlock "Are plus Bre" DstPort 2 } Branch { Points [0, 30] DstBlock "Bre minus Are" DstPort 2 } } Line { SrcBlock "Input1" SrcPort 1 Points [0, 0; 115, 0] Branch { Points [80, 0; 0, -20] DstBlock "Aim plus Bim" DstPort 1 } Branch { Points [0, 185] DstBlock "Bim minus Aim" DstPort 1 } } Line { SrcBlock "Input3" SrcPort 1 Points [0, 0; 105, 0] Branch { Points [90, 0; 0, -155] DstBlock "Aim plus Bim" DstPort 2 } Branch { Points [0, 50] DstBlock "Bim minus Aim" DstPort 2 } } Line { SrcBlock "Are plus Bre" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Aim plus Bim" SrcPort 1 DstBlock "Output1" DstPort 1 } Line { SrcBlock "Bim minus Aim" SrcPort 1 Points [115, 0; 0, -105] DstBlock "Output2" DstPort 1 } Line { SrcBlock "Bre minus Are" SrcPort 1 Points [95, 0; 0, 90] DstBlock "Output3" DstPort 1 } Annotation { Name "Complex butterfly for w^2=-j." Position [454, 21] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } Block { BlockType SubSystem Name "W3 Butterfly 1. stage" Ports [4, 4] Position [390, 481, 485, 559] ForegroundColor "blue" AncestorBlock "ALTELINK/AltLab/HDL SubSystem" FontSize 10 TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "SubSystem AlteraBlockSet" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" System { Name "W3 Butterfly 1. stage" Location [48, 77, 986, 688] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "Are[7:0]" Position [30, 83, 60, 97] ForegroundColor "blue" Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Aim[7:0]" Position [30, 178, 60, 192] ForegroundColor "blue" Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bre[7:0]" Position [30, 258, 60, 272] ForegroundColor "blue" Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "Bim[7:0]" Position [30, 343, 60, 357] ForegroundColor "blue" Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Input" Description "Sign Binary Fractionnal" Ports [1, 1] Position [85, 82, 150, 98] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input" nSgCpl "0" } Block { BlockType Reference Name "Input1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 177, 145, 193] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input1" nSgCpl "0" } Block { BlockType Reference Name "Input2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 257, 145, 273] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input2" nSgCpl "0" } Block { BlockType Reference Name "Input3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [80, 342, 145, 358] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Input3" nSgCpl "0" } Block { BlockType Reference Name "Output" Description "Sign Binary Fractionnal" Ports [1, 1] Position [730, 77, 795, 93] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output1" Description "Sign Binary Fractionnal" Ports [1, 1] Position [730, 172, 795, 188] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output2" Description "Sign Binary Fractionnal" Ports [1, 1] Position [745, 352, 810, 368] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "Output3" Description "Sign Binary Fractionnal" Ports [1, 1] Position [750, 477, 815, 493] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Output" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Output Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "Output" nSgCpl "0" } Block { BlockType Reference Name "c minus s" Description "Sign Binary Fractionnal" Ports [0, 1] Position [85, 521, 135, 539] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Constant" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Constant" bwl "9" bwr "0" sat off rnd off bp off mask_cst "0" ncstsamp "1" cst "0" modulename "Constant" nSgCpl "0" } Block { BlockType Reference Name "c plus s" Description "Sign Binary Fractionnal" Ports [0, 1] Position [85, 466, 135, 484] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Constant" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Constant" bwl "9" bwr "0" sat off rnd off bp off mask_cst "0" ncstsamp "1" cst "0" modulename "Constant" nSgCpl "0" } Block { BlockType Reference Name "cos" Description "Sign Binary Fractionnal" Ports [0, 1] Position [85, 416, 135, 434] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Constant" SourceType "AltBus AlteraBlockSet" sgn "Signed Integer" nodetype "Constant" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" ncstsamp "1" cst "0" modulename "Constant" nSgCpl "0" } Block { BlockType Outport Name "Dre[7:0]" Position [825, 78, 855, 92] ForegroundColor "blue" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Dim[7:0]" Position [825, 173, 855, 187] ForegroundColor "blue" Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Ere[7:0]" Position [840, 353, 870, 367] ForegroundColor "blue" Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Eim[7:0]" Position [845, 478, 875, 492] ForegroundColor "blue" Port "4" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "Aim[7:0]" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "Dre[7:0]" DstPort 1 } Line { SrcBlock "Are[7:0]" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output1" SrcPort 1 DstBlock "Dim[7:0]" DstPort 1 } Line { SrcBlock "Bre[7:0]" SrcPort 1 DstBlock "Input2" DstPort 1 } Line { SrcBlock "Bim[7:0]" SrcPort 1 DstBlock "Input3" DstPort 1 } Line { SrcBlock "Output2" SrcPort 1 DstBlock "Ere[7:0]" DstPort 1 } Line { SrcBlock "Output3" SrcPort 1 DstBlock "Eim[7:0]" DstPort 1 } Annotation { Name "Complex butterfly for w^3=exp(-j*3*\\pi/4)." Position [444, 16] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } } } Block { BlockType Reference Name "Xim0" Ports [1, 1] Position [940, 323, 970, 357] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xim1" Ports [1, 1] Position [940, 358, 970, 392] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xim2" Ports [1, 1] Position [940, 393, 970, 427] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xim3" Ports [1, 1] Position [940, 428, 970, 462] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xim4" Ports [1, 1] Position [940, 463, 970, 497] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xim5" Ports [1, 1] Position [940, 498, 970, 532] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xim6" Ports [1, 1] Position [940, 533, 970, 567] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xim7" Ports [1, 1] Position [940, 568, 970, 602] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xre0" Ports [1, 1] Position [935, 13, 965, 47] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xre1" Ports [1, 1] Position [935, 48, 965, 82] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xre2" Ports [1, 1] Position [935, 83, 965, 117] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xre3" Ports [1, 1] Position [935, 118, 965, 152] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xre4" Ports [1, 1] Position [935, 153, 965, 187] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xre5" Ports [1, 1] Position [935, 188, 965, 222] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xre6" Ports [1, 1] Position [935, 223, 965, 257] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Reference Name "Xre7" Ports [1, 1] Position [935, 258, 965, 292] ForegroundColor "blue" FontSize 10 SourceBlock "store_alteradspbuilder/Delay" SourceType "Delay AlteraBlockSet" depth "1" clken off MaskValue "1" } Block { BlockType Constant Name "x Imag is zero" Position [45, 385, 75, 415] Value "0" } Block { BlockType Reference Name "x Real has \ntriangular" Ports [0, 1] Position [35, 85, 65, 115] SourceBlock "simulink/Sources/Repeating\nSequence" SourceType "Repeating table" ShowPortLabels on rep_seq_t "[0 1 2 3 4 5 6 7 8 9 10 100]" rep_seq_y "[0 0 16 14 12 10 8 6 4 2 0 0]" } Line { SrcBlock "Input Re" SrcPort 1 DstBlock "Shift Taps Real" DstPort 1 } Line { SrcBlock "Pulse\nGenerator" SrcPort 1 DstBlock "Enable" DstPort 1 } Line { SrcBlock "Enable" SrcPort 1 Points [5, 0] Branch { DstBlock "Shift Taps Real" DstPort 2 } Branch { Points [0, 300] DstBlock "Shift Taps Imag" DstPort 2 } } Line { SrcBlock "Input Im" SrcPort 1 DstBlock "Shift Taps Imag" DstPort 1 } Line { SrcBlock "Shift Taps Real" SrcPort 1 DstBlock "W0 Butterfly 1. stage" DstPort 1 } Line { SrcBlock "Shift Taps Imag" SrcPort 1 Points [45, 0; 0, -280] DstBlock "W0 Butterfly 1. stage" DstPort 2 } Line { SrcBlock "Shift Taps Real" SrcPort 5 Points [55, 0; 0, -80] DstBlock "W0 Butterfly 1. stage" DstPort 3 } Line { SrcBlock "Shift Taps Imag" SrcPort 5 Points [65, 0; 0, -360] DstBlock "W0 Butterfly 1. stage" DstPort 4 } Line { SrcBlock "Shift Taps Real" SrcPort 2 Points [20, 0; 0, 105] DstBlock "W1 Butterfly 1.stage" DstPort 1 } Line { SrcBlock "Shift Taps Imag" SrcPort 2 Points [30, 0; 0, -175] DstBlock "W1 Butterfly 1.stage" DstPort 2 } Line { SrcBlock "Shift Taps Real" SrcPort 6 Points [20, 0; 0, 25] DstBlock "W1 Butterfly 1.stage" DstPort 3 } Line { SrcBlock "Shift Taps Imag" SrcPort 6 Points [25, 0; 0, -255] DstBlock "W1 Butterfly 1.stage" DstPort 4 } Line { SrcBlock "Shift Taps Real" SrcPort 3 Points [15, 0; 0, 235] DstBlock "W2 Butterfly 1. stage" DstPort 1 } Line { SrcBlock "Shift Taps Imag" SrcPort 3 Points [35, 0; 0, -45] DstBlock "W2 Butterfly 1. stage" DstPort 2 } Line { SrcBlock "Shift Taps Imag" SrcPort 7 Points [75, 0; 0, -125] DstBlock "W2 Butterfly 1. stage" DstPort 4 } Line { SrcBlock "Shift Taps Real" SrcPort 7 Points [75, 0; 0, 155] DstBlock "W2 Butterfly 1. stage" DstPort 3 } Line { SrcBlock "Shift Taps Real" SrcPort 4 Points [80, 0; 0, 345] DstBlock "W3 Butterfly 1. stage" DstPort 1 } Line { SrcBlock "Shift Taps Imag" SrcPort 4 Points [40, 0; 0, 65] DstBlock "W3 Butterfly 1. stage" DstPort 2 } Line { SrcBlock "Shift Taps Real" SrcPort 8 Points [90, 0; 0, 265] DstBlock "W3 Butterfly 1. stage" DstPort 3 } Line { SrcBlock "Shift Taps Imag" SrcPort 8 Points [0, -15] DstBlock "W3 Butterfly 1. stage" DstPort 4 } Line { SrcBlock "W1 Butterfly 1.stage" SrcPort 1 Points [5, 0; 0, -60] DstBlock "Scope W1" DstPort 1 } Line { SrcBlock "W1 Butterfly 1.stage" SrcPort 2 Points [10, 0; 0, -70] DstBlock "Scope W1" DstPort 2 } Line { SrcBlock "W1 Butterfly 1.stage" SrcPort 3 Points [15, 0; 0, -80] DstBlock "Scope W1" DstPort 3 } Line { SrcBlock "W1 Butterfly 1.stage" SrcPort 4 Points [20, 0; 0, -90] DstBlock "Scope W1" DstPort 4 } Line { SrcBlock "W3 Butterfly 1. stage" SrcPort 1 Points [20, 0; 0, 80] DstBlock "Scope W3" DstPort 1 } Line { SrcBlock "W3 Butterfly 1. stage" SrcPort 2 Points [25, 0; 0, 70] DstBlock "Scope W3" DstPort 2 } Line { SrcBlock "W3 Butterfly 1. stage" SrcPort 3 Points [15, 0; 0, 60] DstBlock "Scope W3" DstPort 3 } Line { SrcBlock "W3 Butterfly 1. stage" SrcPort 4 Points [10, 0; 0, 50] DstBlock "Scope W3" DstPort 4 } Line { SrcBlock "x Real has \ntriangular" SrcPort 1 DstBlock "Input Re" DstPort 1 } Line { SrcBlock "x Imag is zero" SrcPort 1 DstBlock "Input Im" DstPort 1 } Line { SrcBlock "Output Xre0" SrcPort 1 DstBlock "Real Scope" DstPort 1 } Line { SrcBlock "Output Xre1" SrcPort 1 DstBlock "Real Scope" DstPort 2 } Line { SrcBlock "Output Xre2" SrcPort 1 DstBlock "Real Scope" DstPort 3 } Line { SrcBlock "Output Xre3" SrcPort 1 DstBlock "Real Scope" DstPort 4 } Line { SrcBlock "Output Xre4" SrcPort 1 DstBlock "Real Scope" DstPort 5 } Line { SrcBlock "Output Xre5" SrcPort 1 DstBlock "Real Scope" DstPort 6 } Line { SrcBlock "Output Xre6" SrcPort 1 DstBlock "Real Scope" DstPort 7 } Line { SrcBlock "Output Xre7" SrcPort 1 DstBlock "Real Scope" DstPort 8 } Line { SrcBlock "Output Xim0" SrcPort 1 DstBlock "Imag Scope" DstPort 1 } Line { SrcBlock "Output Xim1" SrcPort 1 DstBlock "Imag Scope" DstPort 2 } Line { SrcBlock "Output Xim2" SrcPort 1 DstBlock "Imag Scope" DstPort 3 } Line { SrcBlock "Output Xim3" SrcPort 1 DstBlock "Imag Scope" DstPort 4 } Line { SrcBlock "Output Xim4" SrcPort 1 DstBlock "Imag Scope" DstPort 5 } Line { SrcBlock "Output Xim5" SrcPort 1 DstBlock "Imag Scope" DstPort 6 } Line { SrcBlock "Output Xim7" SrcPort 1 DstBlock "Imag Scope" DstPort 8 } Line { SrcBlock "Output Xim6" SrcPort 1 DstBlock "Imag Scope" DstPort 7 } Line { SrcBlock "Xre0" SrcPort 1 DstBlock "Output Xre0" DstPort 1 } Line { SrcBlock "Xre1" SrcPort 1 DstBlock "Output Xre1" DstPort 1 } Line { SrcBlock "Xre2" SrcPort 1 DstBlock "Output Xre2" DstPort 1 } Line { SrcBlock "Xre3" SrcPort 1 DstBlock "Output Xre3" DstPort 1 } Line { SrcBlock "Xre4" SrcPort 1 DstBlock "Output Xre4" DstPort 1 } Line { SrcBlock "Xre5" SrcPort 1 DstBlock "Output Xre5" DstPort 1 } Line { SrcBlock "Xre6" SrcPort 1 DstBlock "Output Xre6" DstPort 1 } Line { SrcBlock "Xre7" SrcPort 1 DstBlock "Output Xre7" DstPort 1 } Line { SrcBlock "Xim0" SrcPort 1 DstBlock "Output Xim0" DstPort 1 } Line { SrcBlock "Xim1" SrcPort 1 DstBlock "Output Xim1" DstPort 1 } Line { SrcBlock "Xim2" SrcPort 1 DstBlock "Output Xim2" DstPort 1 } Line { SrcBlock "Xim3" SrcPort 1 DstBlock "Output Xim3" DstPort 1 } Line { SrcBlock "Xim4" SrcPort 1 DstBlock "Output Xim4" DstPort 1 } Line { SrcBlock "Xim5" SrcPort 1 DstBlock "Output Xim5" DstPort 1 } Line { SrcBlock "Xim6" SrcPort 1 DstBlock "Output Xim6" DstPort 1 } Line { SrcBlock "Xim7" SrcPort 1 DstBlock "Output Xim7" DstPort 1 } Annotation { Name "1. stage" Position [429, 21] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } Annotation { Name "2. stage" Position [639, 21] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } Annotation { Name "3. stage" Position [809, 21] DropShadow on TeXMode "on" FontName "Arial" FontSize 12 FontWeight "bold" } Annotation { Position [25, 441] } } }