EEL 4710 - Introduction to Field Programmable Logic Devices

Curriculum Designation: Required course for computer engineering majors. Tier II Elective course for electrical engineering majors.

Course Description: This course offers an overview of programmable logic devices, complex programmable logic devices, and field-programmable gate-array devices. The course offers an introduction to hardware description languages (HDLs); combinational, sequential, and finite-state machine design using HDLs; as well as top-down methodologies.

Prerequisites: EEL 3705 and EEL 3705L

Course Objectives:

  1. Design a combinatorial digital logic circuit using a hardware description language (HDL).
  2. Design a finite-state machine (FSM) using a HDL.
  3. Synthesize a gate-level digital logic circuit from HDL code using a gate-level cell library.
  4. Analyze a gate-level digital logic circuit and develop its equivalent HDL code.
  5. Verify the design implementation of a FSM using computer simulation.
  6. Determine the maximum switching frequency of a sequential circuit.
  7. Discuss and describe the differences and design tradeoffs between different FPLD architectures.
  8. Analyze contemporary issues in FPLD project design.
  9. Recognize the need for lifelong learning and engage in lifelong learning.

Topics Covered:

  1. Review of digital logic fundamentals
  2. Intro to VHSIC Hardware Description Language (VHDL)
  3. Combinatorial and synchronous logic design using VHDL.
  4. Introduction to Field Programmable Logic Devices (FPLDs)
  5. System design methodologies.
  6. Advanced logic design topics

Class Schedule: Three 50 minute or two 75 minute lectures per week (3 credit hours).

Contribution to Professional Component: Engineering topic: 3 credit hours

Science/Design (%): 50% / 50%

Relationship to ABET Program Outcomes: A, C, E, H, I, J, K and O(CpE)

Prepared by: Linda DeBrunner